4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S debug support (implementation).
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/macros.h> /* for BV() */
39 #include "kdebug_lm3s.h"
40 #include "clock_lm3s.h" /* __delay() */
41 #include "cfg/cfg_debug.h"
43 #include "gpio_lm3s.h"
45 INLINE void uart_disable(size_t base)
47 /* Disable the FIFO */
48 HWREG(base + UART_O_LCRH) &= ~UART_LCRH_FEN;
49 /* Disable the UART */
50 HWREG(base + UART_O_CTL) &=
51 ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
54 INLINE void uart_enable(size_t base)
57 HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN;
58 /* Enable RX, TX, and the UART */
59 HWREG(base + UART_O_CTL) |=
60 UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
63 INLINE void uart_config(size_t base, uint32_t baud, reg32_t config)
68 if (baud * 16 > CPU_FREQ)
73 div = (CPU_FREQ * 8 / baud + 1) / 2;
78 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
80 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
82 /* Set the baud rate */
83 HWREG(base + UART_O_IBRD) = div / 64;
84 HWREG(base + UART_O_FBRD) = div % 64;
86 /* Set parity, data length, and number of stop bits. */
87 HWREG(base + UART_O_LCRH) = config;
89 /* Clear the flags register */
90 HWREG(base + UART_O_FR) = 0;
95 INLINE bool uart_putchar(size_t base, unsigned char ch)
97 if (!(HWREG(base + UART_O_FR) & UART_FR_TXFF))
99 HWREG(base + UART_O_DR) = ch;
105 #if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
106 #define KDBG_WAIT_READY() while (HWREG(UART0_BASE + UART_O_FR) & UART_FR_BUSY) {}
107 #define KDBG_WAIT_TXDONE() while (!(HWREG(UART0_BASE + UART_O_FR) & UART_FR_TXFE)) {}
109 #define KDBG_WRITE_CHAR(c) do { HWREG(UART0_BASE + UART_O_DR) = c; } while(0)
111 /* Debug unit is used only for debug purposes so does not generate interrupts. */
112 #define KDBG_MASK_IRQ(old) do { (void)old; } while(0)
114 /* Debug unit is used only for debug purposes so does not generate interrupts. */
115 #define KDBG_RESTORE_IRQ(old) do { (void)old; } while(0)
117 typedef uint32_t kdbg_irqsave_t;
120 #error CONFIG_KDEBUG_PORT should be KDEBUG_PORT_DBGU
123 INLINE void kdbg_hw_init(void)
125 /* Enable the peripheral clock */
126 SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
127 SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
129 /* Set GPIO A0 and A1 as UART pins */
130 lm3s_gpio_pin_config(GPIO_PORTA_BASE, BV(0) | BV(1),
131 GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
132 /* 115.200, 8-bit word, no parity, one stop bit */
133 uart_config(UART0_BASE, CONFIG_KDEBUG_BAUDRATE, UART_LCRH_WLEN_8);