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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S debug support (implementation).
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/macros.h> /* for BV() */
39 #include "kdebug_lm3s.h"
40 #include "cfg/cfg_debug.h"
43 INLINE void uart_disable(size_t base)
45 /* Disable the FIFO */
46 HWREG(base + UART_O_LCRH) &= ~UART_LCRH_FEN;
47 /* Disable the UART */
48 HWREG(base + UART_O_CTL) &=
49 ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
52 INLINE void uart_enable(size_t base)
55 HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN;
56 /* Enable RX, TX, and the UART */
57 HWREG(base + UART_O_CTL) |=
58 UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
61 INLINE void uart_config(size_t base, uint32_t baud, reg32_t config)
66 if (baud * 16 > CPU_FREQ)
71 div = (CPU_FREQ * 8 / baud + 1) / 2;
76 HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
78 HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
80 /* Set the baud rate */
81 HWREG(base + UART_O_IBRD) = div / 64;
82 HWREG(base + UART_O_FBRD) = div % 64;
84 /* Set parity, data length, and number of stop bits. */
85 HWREG(base + UART_O_LCRH) = config;
87 /* Clear the flags register */
88 HWREG(base + UART_O_FR) = 0;
93 INLINE bool uart_putchar(size_t base, unsigned char ch)
95 if (!(HWREG(base + UART_O_FR) & UART_FR_TXFF))
97 HWREG(base + UART_O_DR) = ch;
103 #if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
104 #define KDBG_WAIT_READY() while (HWREG(UART0_BASE + UART_O_FR) & UART_FR_BUSY) {}
105 #define KDBG_WAIT_TXDONE() while (!(HWREG(UART0_BASE + UART_O_FR) & UART_FR_TXFE)) {}
107 #define KDBG_WRITE_CHAR(c) do { HWREG(UART0_BASE + UART_O_DR) = c; } while(0)
109 /* Debug unit is used only for debug purposes so does not generate interrupts. */
110 #define KDBG_MASK_IRQ(old) do { (void)old; } while(0)
112 /* Debug unit is used only for debug purposes so does not generate interrupts. */
113 #define KDBG_RESTORE_IRQ(old) do { (void)old; } while(0)
115 typedef uint32_t kdbg_irqsave_t;
118 #error CONFIG_KDEBUG_PORT should be KDEBUG_PORT_DBGU
121 INLINE void kdbg_hw_init(void)
123 /* Enable the peripheral clock */
124 SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
125 SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
127 /* Set GPIO A0 and A1 as UART pins */
128 HWREG(GPIO_PORTA_BASE + GPIO_O_DIR) |= BV(0) | BV(1);
129 HWREG(GPIO_PORTA_BASE + GPIO_O_AFSEL) |= BV(0) | BV(1);
130 HWREG(GPIO_PORTA_BASE + GPIO_O_DR2R) |= BV(0) | BV(1);
131 HWREG(GPIO_PORTA_BASE + GPIO_O_DEN) |= BV(0) | BV(1);
132 HWREG(GPIO_PORTA_BASE + GPIO_O_AMSEL) &= ~(BV(0) | BV(1));
134 /* 115.200, 8-bit word, no parity, one stop bit */
135 uart_config(UART0_BASE, CONFIG_KDEBUG_BAUDRATE, UART_LCRH_WLEN_8);