4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \author Daniele Basile <asterix@develer.com>
35 * SAM3 Analog to Digital Converter.
45 /** ADC registers base. */
46 #define ADC_BASE 0x400C0000
49 * ADC control register
52 #define ADC_CR_OFF 0x00000000 ///< Control register offeset.
53 #define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address.
54 #define ADC_SWRST 0 ///< Software reset.
55 #define ADC_START 1 ///< Start conversion.
62 #define ADC_MR_OFF 0x00000004 ///< Mode register offeset.
63 #define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address.
64 #define ADC_TRGEN 0 ///< Trigger enable.
66 #define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0.
67 #define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1.
68 #define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2.
69 #define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0.
70 #define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1.
72 #define ADC_LOWRES 4 ///< Resolution 0: 12-bit, 1: 10-bit.
73 #define ADC_SLEEP 5 ///< Sleep mode.
74 #define ADC_FREERUN 7 ///< Freerun.
77 * Prescaler rate selection.
78 * ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2)
80 #define ADC_PRESCALER_MASK 0x0000FF00 ///< Prescaler rate selection mask.
81 #define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift.
86 #define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask.
87 #define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
91 * $WIZ$ sam3_adc_sut = "ADC_SUT0","ADC_SUT8","ADC_SUT16","ADC_SUT24","ADC_SUT64","DC_SUT80","ADC_SUT96","ADC_SUT112","ADC_SUT512","ADC_SUT576","ADC_SUT640","ADC_SUT704","ADC_SUT768","ADC_SUT832","ADC_SUT896","ADC_SUT960"
94 #define ADC_SUT0 0 ///< 0 period of ADCClock.
95 #define ADC_SUT8 1 ///< 8 period of ADCClock.
96 #define ADC_SUT16 2 ///< 16 period of ADCClock.
97 #define ADC_SUT24 3 ///< 24 period of ADCClock.
98 #define ADC_SUT64 4 ///< 64 period of ADCClock.
99 #define ADC_SUT80 5 ///< 80 period of ADCClock.
100 #define ADC_SUT96 6 ///< 96 period of ADCClock.
101 #define ADC_SUT112 7 ///< 112 period of ADCClock.
102 #define ADC_SUT512 8 ///< 512 period of ADCClock.
103 #define ADC_SUT576 9 ///< 576 period of ADCClock.
104 #define ADC_SUT640 10 ///< 640 period of ADCClock.
105 #define ADC_SUT704 11 ///< 704 period of ADCClock.
106 #define ADC_SUT768 12 ///< 768 period of ADCClock.
107 #define ADC_SUT832 13 ///< 832 period of ADCClock.
108 #define ADC_SUT896 14 ///< 896 period of ADCClock.
109 #define ADC_SUT960 15 ///< 896 period of ADCClock.
113 * Analog Settling Time.
114 * $WIZ$ sam3_adc_stt = "ADC_AST3", "ADC_AST5", "ADC_AST9", "ADC_AST17"
116 #define ADC_SETTLING_MASK 0x00300000 ///< Analog Settling Time mask.
117 #define ADC_SETTLING_SHIFT 20 ///< Analog Settling Time shift.
118 #define ADC_AST3 0 ///< 3 period of ADCClock
119 #define ADC_AST5 1 ///< 5 period of ADCClock
120 #define ADC_AST9 2 ///< 9 period of ADCClock
121 #define ADC_AST17 3 ///< 17 period of ADCClock
125 * Tracking Time = (TRACKTIM + 1) * ADCClock periods.
127 #define ADC_TRACKTIM_MASK 0x0F000000 ///< Tracking Time mask.
128 #define ADC_TRACKTIM_SHIFT 24 ///< Tracking Time shift.
132 * Transfer Period = (TRANSFER * 2 + 3) ADCClock periods.
134 #define ADC_TRANSFER_MASK 0x30000000 ///< Transfer Period mask.
135 #define ADC_TRANSFER_SHIFT 28 ///< Transfer Period shift.
140 * ADC channel enable register
142 #define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
143 #define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address.
146 * ADC channel disable register
148 #define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
149 #define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address.
152 * ADC channel status register
154 #define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
155 #define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address.
159 * ADC status register
161 #define ADC_SR_OFF 0x0000001C ///< Status register offeset.
162 #define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address.
165 #define ADC_CH_MASK 0x0000FFFF ///< Channel mask.
166 #define ADC_CH0 0 ///< Channel 0
167 #define ADC_CH1 1 ///< Channel 1
168 #define ADC_CH2 2 ///< Channel 2
169 #define ADC_CH3 3 ///< Channel 3
170 #define ADC_CH4 4 ///< Channel 4
171 #define ADC_CH5 5 ///< Channel 5
172 #define ADC_CH6 6 ///< Channel 6
173 #define ADC_CH7 7 ///< Channel 7
176 * ADC Interrupt enable register.
178 #define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
179 #define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register.
182 * ADC Interrupt disable register.
184 #define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
185 #define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register.
188 * ADC Interrupt mask register.
190 #define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset.
191 #define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register.
194 * ADC Interrupt status register.
196 #define ADC_ISR_OFF 0x00000030 ///< Interrupt status register offeset.
197 #define ADC_ISR (*((reg32_t *)(ADC_BASE + ADC_ISR_OFF))) ///< Interrupt status register.
199 #define ADC_EOC_MASK 0x000000FF ///< End of converison mask.
200 #define ADC_EOC0 0 ///< End of conversion channel 0.
201 #define ADC_EOC1 1 ///< End of conversion channel 1.
202 #define ADC_EOC2 2 ///< End of conversion channel 2.
203 #define ADC_EOC3 3 ///< End of conversion channel 3.
204 #define ADC_EOC4 4 ///< End of conversion channel 4.
205 #define ADC_EOC5 5 ///< End of conversion channel 5.
206 #define ADC_EOC6 6 ///< End of conversion channel 6.
207 #define ADC_EOC7 7 ///< End of conversion channel 7.
209 #define ADC_OVRE0 8 ///< Overrun error channel 0.
210 #define ADC_OVRE1 9 ///< Overrun error channel 1.
211 #define ADC_OVRE2 10 ///< Overrun error channel 2.
212 #define ADC_OVRE3 11 ///< Overrun error channel 3.
213 #define ADC_OVRE4 12 ///< Overrun error channel 4.
214 #define ADC_OVRE5 13 ///< Overrun error channel 5.
215 #define ADC_OVRE6 14 ///< Overrun error channel 6.
216 #define ADC_OVRE7 15 ///< Overrun error channel 7.
218 #define ADC_DRDY 24 ///< Data ready.
219 #define ADC_GOVRE 25 ///< General overrun error.
220 #define ADC_COMPE 26 ///< Comparition event interrupt mask.
221 #define ADC_ENDRX 27 ///< End of RX buffer.
222 #define ADC_RXBUFF 28 ///< Rx buffer full.
225 * ADC last convert data register.
228 #define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset.
229 #define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted RAW data register.
230 #define ADC_LDATA (ADC_LCDR & 0xFFF) ///< Last data converted register.
231 #define ADC_CHNB ((ADC_LCDR & 0xF000) >> 12) ///< Channel number.
236 * ADC Channel data register.
239 #define ADC_CDR_OFF 0x00000050 ///< Channel data register offeset.
240 #define ADC_CDR (*((reg32_t *)(ADC_BASE + ADC_CDR_OFF))) ///< Channel data register.
245 * ADC Analog Control register.
248 #define ADC_ACR_OFF 0x00000094 ///< Analog control register offeset.
249 #define ADC_ACR (*((reg32_t *)(ADC_BASE + ADC_ACR_OFF))) ///< Analog control register.
250 #define ADC_TSON 4 ///< Temperature Sensor On.
251 #define ADC_TEMPERATURE_CH 15 ///< Channel where is the internal sensor temperature
254 #endif /* SAM3_ADC_H */