4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007,2010 Develer S.r.l. (http://www.develer.com/)
34 * \author Francesco Sacchi <batt@develer.com>
36 * Atmel SAM3 Parallel input/output controller.
37 * This file is based on NUT/OS implementation. See license below.
41 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
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51 * documentation and/or other materials provided with the distribution.
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53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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59 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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69 * For additional information see http://www.ethernut.de/
76 * PIO registers base addresses.
79 #define PIOA_BASE 0x400E0E00
80 #define PIOB_BASE 0x400E1000
81 #define PIOC_BASE 0x400E1200
84 #define PIOD_BASE 0x400E1400
85 #define PIOE_BASE 0x400E1600
86 #define PIOF_BASE 0x400E1800
90 /** PIO Register Offsets */
92 #define PIO_PER_OFF 0x00000000 ///< PIO enable register offset.
93 #define PIO_PDR_OFF 0x00000004 ///< PIO disable register offset.
94 #define PIO_PSR_OFF 0x00000008 ///< PIO status register offset.
95 #define PIO_OER_OFF 0x00000010 ///< Output enable register offset.
96 #define PIO_ODR_OFF 0x00000014 ///< Output disable register offset.
97 #define PIO_OSR_OFF 0x00000018 ///< Output status register offset.
98 #define PIO_IFER_OFF 0x00000020 ///< Input filter enable register offset.
99 #define PIO_IFDR_OFF 0x00000024 ///< Input filter disable register offset.
100 #define PIO_IFSR_OFF 0x00000028 ///< Input filter status register offset.
101 #define PIO_SODR_OFF 0x00000030 ///< Set output data register offset.
102 #define PIO_CODR_OFF 0x00000034 ///< Clear output data register offset.
103 #define PIO_ODSR_OFF 0x00000038 ///< Output data status register offset.
104 #define PIO_PDSR_OFF 0x0000003C ///< Pin data status register offset.
105 #define PIO_IER_OFF 0x00000040 ///< Interrupt enable register offset.
106 #define PIO_IDR_OFF 0x00000044 ///< Interrupt disable register offset.
107 #define PIO_IMR_OFF 0x00000048 ///< Interrupt mask register offset.
108 #define PIO_ISR_OFF 0x0000004C ///< Interrupt status register offset.
109 #define PIO_MDER_OFF 0x00000050 ///< Multi-driver enable register offset.
110 #define PIO_MDDR_OFF 0x00000054 ///< Multi-driver disable register offset.
111 #define PIO_MDSR_OFF 0x00000058 ///< Multi-driver status register offset.
112 #define PIO_PUDR_OFF 0x00000060 ///< Pull-up disable register offset.
113 #define PIO_PUER_OFF 0x00000064 ///< Pull-up enable register offset.
114 #define PIO_PUSR_OFF 0x00000068 ///< Pull-up status register offset.
115 #define PIO_ABCDSR1_OFF 0x00000070 ///< PIO peripheral select register 1 offset.
116 #define PIO_ABCDSR2_OFF 0x00000074 ///< PIO peripheral select register 2 offset.
117 #define PIO_OWER_OFF 0x000000A0 ///< PIO output write enable register offset.
118 #define PIO_OWDR_OFF 0x000000A4 ///< PIO output write disable register offset.
119 #define PIO_OWSR_OFF 0x000000A8 ///< PIO output write status register offset.
122 /** Single PIO Register Addresses */
124 #if defined(PIO_BASE)
125 #define PIO_ACCESS(offset) (*((reg32_t *)(PIO_BASE + (offset))))
127 #define PIO_PER PIO_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
128 #define PIO_PDR PIO_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
129 #define PIO_PSR PIO_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
130 #define PIO_OER PIO_ACCESS(PIO_OER_OFF) ///< Output enable register address.
131 #define PIO_ODR PIO_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
132 #define PIO_OSR PIO_ACCESS(PIO_OSR_OFF) ///< Output status register address.
133 #define PIO_IFER PIO_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
134 #define PIO_IFDR PIO_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
135 #define PIO_IFSR PIO_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
136 #define PIO_SODR PIO_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
137 #define PIO_CODR PIO_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
138 #define PIO_ODSR PIO_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
139 #define PIO_PDSR PIO_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
140 #define PIO_IER PIO_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
141 #define PIO_IDR PIO_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
142 #define PIO_IMR PIO_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
143 #define PIO_ISR PIO_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
144 #define PIO_MDER PIO_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
145 #define PIO_MDDR PIO_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
146 #define PIO_MDSR PIO_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
147 #define PIO_PUDR PIO_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
148 #define PIO_PUER PIO_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
149 #define PIO_PUSR PIO_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
150 #define PIO_ABCDSR1 PIO_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
151 #define PIO_ABCDSR2 PIO_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
152 #define PIO_OWER PIO_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
153 #define PIO_OWDR PIO_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
154 #define PIO_OWSR PIO_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
155 #endif /* PIO_BASE */
158 /** PIO A Register Addresses */
160 #if defined(PIOA_BASE)
161 #define PIOA_ACCESS(offset) (*((reg32_t *)(PIOA_BASE + (offset))))
163 #define PIOA_PER PIOA_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
164 #define PIOA_PDR PIOA_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
165 #define PIOA_PSR PIOA_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
166 #define PIOA_OER PIOA_ACCESS(PIO_OER_OFF) ///< Output enable register address.
167 #define PIOA_ODR PIOA_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
168 #define PIOA_OSR PIOA_ACCESS(PIO_OSR_OFF) ///< Output status register address.
169 #define PIOA_IFER PIOA_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
170 #define PIOA_IFDR PIOA_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
171 #define PIOA_IFSR PIOA_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
172 #define PIOA_SODR PIOA_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
173 #define PIOA_CODR PIOA_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
174 #define PIOA_ODSR PIOA_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
175 #define PIOA_PDSR PIOA_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
176 #define PIOA_IER PIOA_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
177 #define PIOA_IDR PIOA_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
178 #define PIOA_IMR PIOA_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
179 #define PIOA_ISR PIOA_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
180 #define PIOA_MDER PIOA_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
181 #define PIOA_MDDR PIOA_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
182 #define PIOA_MDSR PIOA_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
183 #define PIOA_PUDR PIOA_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
184 #define PIOA_PUER PIOA_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
185 #define PIOA_PUSR PIOA_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
186 #define PIOA_ABCDSR1 PIOA_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
187 #define PIOA_ABCDSR2 PIOA_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
188 #define PIOA_OWER PIOA_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
189 #define PIOA_OWDR PIOA_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
190 #define PIOA_OWSR PIOA_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
191 #endif /* PIOA_BASE */
194 /** PIO B Register Addresses */
196 #if defined(PIOB_BASE)
197 #define PIOB_ACCESS(offset) (*((reg32_t *)(PIOB_BASE + (offset))))
199 #define PIOB_PER PIOB_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
200 #define PIOB_PDR PIOB_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
201 #define PIOB_PSR PIOB_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
202 #define PIOB_OER PIOB_ACCESS(PIO_OER_OFF) ///< Output enable register address.
203 #define PIOB_ODR PIOB_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
204 #define PIOB_OSR PIOB_ACCESS(PIO_OSR_OFF) ///< Output status register address.
205 #define PIOB_IFER PIOB_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
206 #define PIOB_IFDR PIOB_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
207 #define PIOB_IFSR PIOB_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
208 #define PIOB_SODR PIOB_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
209 #define PIOB_CODR PIOB_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
210 #define PIOB_ODSR PIOB_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
211 #define PIOB_PDSR PIOB_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
212 #define PIOB_IER PIOB_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
213 #define PIOB_IDR PIOB_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
214 #define PIOB_IMR PIOB_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
215 #define PIOB_ISR PIOB_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
216 #define PIOB_MDER PIOB_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
217 #define PIOB_MDDR PIOB_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
218 #define PIOB_MDSR PIOB_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
219 #define PIOB_PUDR PIOB_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
220 #define PIOB_PUER PIOB_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
221 #define PIOB_PUSR PIOB_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
222 #define PIOB_ABCDSR1 PIOB_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
223 #define PIOB_ABCDSR2 PIOB_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
224 #define PIOB_OWER PIOB_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
225 #define PIOB_OWDR PIOB_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
226 #define PIOB_OWSR PIOB_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
227 #endif /* PIOB_BASE */
230 /** PIO C Register Addresses */
232 #if defined(PIOC_BASE)
233 #define PIOC_ACCESS(offset) (*((reg32_t *)(PIOC_BASE + (offset))))
235 #define PIOC_PER PIOC_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
236 #define PIOC_PDR PIOC_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
237 #define PIOC_PSR PIOC_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
238 #define PIOC_OER PIOC_ACCESS(PIO_OER_OFF) ///< Output enable register address.
239 #define PIOC_ODR PIOC_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
240 #define PIOC_OSR PIOC_ACCESS(PIO_OSR_OFF) ///< Output status register address.
241 #define PIOC_IFER PIOC_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
242 #define PIOC_IFDR PIOC_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
243 #define PIOC_IFSR PIOC_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
244 #define PIOC_SODR PIOC_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
245 #define PIOC_CODR PIOC_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
246 #define PIOC_ODSR PIOC_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
247 #define PIOC_PDSR PIOC_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
248 #define PIOC_IER PIOC_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
249 #define PIOC_IDR PIOC_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
250 #define PIOC_IMR PIOC_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
251 #define PIOC_ISR PIOC_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
252 #define PIOC_MDER PIOC_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
253 #define PIOC_MDDR PIOC_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
254 #define PIOC_MDSR PIOC_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
255 #define PIOC_PUDR PIOC_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
256 #define PIOC_PUER PIOC_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
257 #define PIOC_PUSR PIOC_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
258 #define PIOC_ABCDSR1 PIOC_ACCESS(PIO_ABCDSR1_OFF) ///< PIO peripheral select register 1 address.
259 #define PIOC_ABCDSR2 PIOC_ACCESS(PIO_ABCDSR2_OFF) ///< PIO peripheral select register 2 address.
260 #define PIOC_OWER PIOC_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
261 #define PIOC_OWDR PIOC_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
262 #define PIOC_OWSR PIOC_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
263 #endif /* PIOC_BASE */
266 #endif /* SAM3_PIO_H */