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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief SAM3 PMC hardware.
39 #include <cfg/macros.h>
40 #include <cfg/debug.h>
43 /** PMC registers base. */
45 #define PMC_BASE 0x400E0600
47 #define PMC_BASE 0x400E0400
51 * PMC register offsets.
54 #define PMC_SCER_OFF 0x00 ///< System Clock Enable Register
55 #define PMC_SCDR_OFF 0x04 ///< System Clock Disable Register
56 #define PMC_SCSR_OFF 0x08 ///< System Clock Status Register
57 #define PMC_MOR_OFF 0x20 ///< Main Oscillator Register
58 #define PMC_MCFR_OFF 0x24 ///< Main Clock Frequency Register
59 #define PMC_MCKR_OFF 0x30 ///< Master Clock Register
60 #define PMC_IER_OFF 0x60 ///< Interrupt Enable Register
61 #define PMC_IDR_OFF 0x64 ///< Interrupt Disable Register
62 #define PMC_SR_OFF 0x68 ///< Status Register
63 #define PMC_IMR_OFF 0x6C ///< Interrupt Mask Register
64 #define PMC_FSMR_OFF 0x70 ///< Fast Startup Mode Register
65 #define PMC_FSPR_OFF 0x74 ///< Fast Startup Polarity Register
66 #define PMC_FOCR_OFF 0x78 ///< Fault Output Clear Register
67 #define PMC_WPMR_OFF 0xE4 ///< Write Protect Mode Register
68 #define PMC_WPSR_OFF 0xE8 ///< Write Protect Status Register
71 #define PMC_PCER_OFF 0x10 ///< Peripheral Clock Enable Register
72 #define PMC_PCDR_OFF 0x14 ///< Peripheral Clock Disable Register
73 #define PMC_PCSR_OFF 0x18 ///< Peripheral Clock Status Register
74 #define PMC_PLLR_OFF 0x28 ///< PLL Register
75 #define PMC_PCK_OFF 0x40 ///< Programmable Clock 0 Register
76 #define PMC_OCR_OFF 0x110 ///< Oscillator Calibration Register
78 #define PMC_PCER0_OFF 0x10 ///< Peripheral Clock Enable Register
79 #define PMC_PCDR0_OFF 0x14 ///< Peripheral Clock Disable Register
80 #define PMC_PCSR0_OFF 0x18 ///< Peripheral Clock Status Register
81 #define PMC_UCKR_OFF 0x1C ///< UTMI clock register
82 #define PMC_PLLAR_OFF 0x28 ///< PLL Register
83 #define PMC_USB_OFF 0x38 ///< USB clock register
84 #define PMC_PCK0_OFF 0x40 ///< Programmable Clock 0 Register
85 #define PMC_PCK1_OFF 0x44 ///< Programmable Clock 1 Register
86 #define PMC_PCK2_OFF 0x48 ///< Programmable Clock 2 Register
87 #define PMC_PCER1_OFF 0x100 ///< Peripheral Clock Enable Register
88 #define PMC_PCDR1_OFF 0x104 ///< Peripheral Clock Disable Register
89 #define PMC_PCSR1_OFF 0x108 ///< Peripheral Clock Status Register
90 #define PMC_PCR_OFF 0x10C ///< Oscillator Calibration Register
92 #define PMC_PLLROFF PMC_PLLAR_OFF
94 #warning Some PMC registers undefined for the selected CPU
102 #define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System Clock Enable Register
103 #define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System Clock Disable Register
104 #define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System Clock Status Register
105 #define CKGR_MOR (*((reg32_t *)(PMC_BASE + PMC_MOR_OFF ))) ///< Main Oscillator Register
106 #define CKGR_MCFR (*((reg32_t *)(PMC_BASE + PMC_MCFR_OFF))) ///< Main Clock Frequency Register
107 #define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master Clock Register
108 #define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF ))) ///< Interrupt Enable Register
109 #define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF ))) ///< Interrupt Disable Register
110 #define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF ))) ///< Status Register
111 #define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF ))) ///< Interrupt Mask Register
112 #define PMC_FSMR (*((reg32_t *)(PMC_BASE + PMC_FSMR_OFF))) ///< Fast Startup Mode Register
113 #define PMC_FSPR (*((reg32_t *)(PMC_BASE + PMC_FSPR_OFF))) ///< Fast Startup Polarity Register
114 #define PMC_FOCR (*((reg32_t *)(PMC_BASE + PMC_FOCR_OFF))) ///< Fault Output Clear Register
115 #define PMC_WPMR (*((reg32_t *)(PMC_BASE + PMC_WPMR_OFF))) ///< Write Protect Mode Register
116 #define PMC_WPSR (*((reg32_t *)(PMC_BASE + PMC_WPSR_OFF))) ///< Write Protect Status Register
119 #define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral Clock Enable Register
120 #define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral Clock Disable Register
121 #define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral Clock Status Register
122 #define CKGR_PLLR (*((reg32_t *)(PMC_BASE + PMC_PLLR_OFF))) ///< PLL Register
123 #define PMC_PCK (*((reg32_t *)(PMC_BASE + PMC_PCK_OFF ))) ///< Programmable Clock 0 Register
124 #define PMC_OCR (*((reg32_t *)(PMC_BASE + PMC_OCR_OFF ))) ///< Oscillator Calibration Register
126 #define PMC_PCER0 (*((reg32_t *)(PMC_BASE + PMC_PCER0_OFF))) ///< Peripheral Clock Enable Register
127 #define PMC_PCDR0 (*((reg32_t *)(PMC_BASE + PMC_PCDR0_OFF))) ///< Peripheral Clock Disable Register
128 #define PMC_PCSR0 (*((reg32_t *)(PMC_BASE + PMC_PCSR0_OFF))) ///< Peripheral Clock Status Register
129 #define PMC_UCKR (*((reg32_t *)(PMC_BASE + PMC_UCKR _OFF))) ///< UTMI clock register
130 #define CKGR_PLLAR (*((reg32_t *)(PMC_BASE + PMC_PLLAR_OFF))) ///< PLL Register
131 #define PMC_USB_O (*((reg32_t *)(PMC_BASE + PMC_USB_O_OFF))) ///< USB clock register
132 #define PMC_PCK0 (*((reg32_t *)(PMC_BASE + PMC_PCK0 _OFF))) ///< Programmable Clock 0 Register
133 #define PMC_PCK1 (*((reg32_t *)(PMC_BASE + PMC_PCK1 _OFF))) ///< Programmable Clock 1 Register
134 #define PMC_PCK2 (*((reg32_t *)(PMC_BASE + PMC_PCK2 _OFF))) ///< Programmable Clock 2 Register
135 #define PMC_PCER1 (*((reg32_t *)(PMC_BASE + PMC_PCER1_OFF))) ///< Peripheral Clock Enable Register
136 #define PMC_PCDR1 (*((reg32_t *)(PMC_BASE + PMC_PCDR1_OFF))) ///< Peripheral Clock Disable Register
137 #define PMC_PCSR1 (*((reg32_t *)(PMC_BASE + PMC_PCSR1_OFF))) ///< Peripheral Clock Status Register
138 #define PMC_PCR (*((reg32_t *)(PMC_BASE + PMC_PCR _OFF))) ///< Oscillator Calibration Register
140 #define CKGR_PLLR CKGR_PLLAR
145 * Enable a peripheral clock.
147 * \param id peripheral id of the peripheral whose clock is enabled
151 INLINE void pmc_periphEnable(unsigned id)
157 PMC_PCER1 = BV(id - 32);
162 INLINE void pmc_periphEnable(unsigned id)
171 * Disable a peripheral clock.
173 * \param id peripheral id of the peripheral whose clock is enabled
177 INLINE void pmc_periphDisable(unsigned id)
183 PMC_PCDR1 = BV(id - 32);
188 INLINE void pmc_periphDisable(unsigned id)
197 * Defines for bit fields in PMC_SCER register.
200 #define PMC_SCER_PCK0 8 ///< Programmable Clock 0 Output Enable
201 #define PMC_SCER_PCK1 9 ///< Programmable Clock 1 Output Enable
202 #define PMC_SCER_PCK2 10 ///< Programmable Clock 2 Output Enable
206 * Defines for bit fields in PMC_SCDR register.
209 #define PMC_SCDR_PCK0 8 ///< Programmable Clock 0 Output Disable
210 #define PMC_SCDR_PCK1 9 ///< Programmable Clock 1 Output Disable
211 #define PMC_SCDR_PCK2 10 ///< Programmable Clock 2 Output Disable
215 * Defines for bit fields in PMC_SCSR register.
218 #define PMC_SCSR_PCK0 8 ///< Programmable Clock 0 Output Status
219 #define PMC_SCSR_PCK1 9 ///< Programmable Clock 1 Output Status
220 #define PMC_SCSR_PCK2 10 ///< Programmable Clock 2 Output Status
224 * Defines for bit fields in CKGR_MOR register.
227 #define CKGR_MOR_MOSCXTEN 0 ///< Main Crystal Oscillator Enable
228 #define CKGR_MOR_MOSCXTBY 1 ///< Main Crystal Oscillator Bypass
229 #define CKGR_MOR_WAITMODE 2 ///< Wait Mode Command
230 #define CKGR_MOR_MOSCRCEN 3 ///< Main On-Chip RC Oscillator Enable
231 #define CKGR_MOR_MOSCRCF_SHIFT 4
232 #define CKGR_MOR_MOSCRCF_MASK (0x7 << CKGR_MOR_MOSCRCF_SHIFT) ///< Main On-Chip RC Oscillator Frequency Selection
233 #define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))
234 #define CKGR_MOR_MOSCRCF_4MHZ (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
235 #define CKGR_MOR_MOSCRCF_8MHZ (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
236 #define CKGR_MOR_MOSCRCF_12MHZ (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
237 #define CKGR_MOR_MOSCXTST_SHIFT 8
238 #define CKGR_MOR_MOSCXTST_MASK (0xff << CKGR_MOR_MOSCXTST_SHIFT) ///< Main Crystal Oscillator Start-up Time
239 #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))
240 #define CKGR_MOR_KEY_SHIFT 16
241 #define CKGR_MOR_KEY_MASK (0xffu << CKGR_MOR_KEY_SHIFT) ///< Password
242 #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_MASK & ((value) << CKGR_MOR_KEY_SHIFT)))
243 #define CKGR_MOR_MOSCSEL 24 ///< Main Oscillator Selection
244 #define CKGR_MOR_CFDEN 25 ///< Clock Failure Detector Enable
248 * Defines for bit fields in CKGR_MCFR register.
251 #define CKGR_MCFR_MAINF_MASK 0xffff ///< Main Clock Frequency mask
252 #define CKGR_MCFR_MAINFRDY 16 ///< Main Clock Ready
256 * Defines for bit fields in CKGR_PLLR register.
259 #define CKGR_PLLR_DIV_MASK 0xff ///< Divider mask
260 #define CKGR_PLLR_DIV(value) (CKGR_PLLR_DIV_MASK & (value))
261 #define CKGR_PLLR_PLLCOUNT_SHIFT 8
262 #define CKGR_PLLR_PLLCOUNT_MASK (0x3f << CKGR_PLLR_PLLCOUNT_SHIFT) ///< PLL Counter mask
263 #define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_MASK & ((value) << CKGR_PLLR_PLLCOUNT_SHIFT))
264 #define CKGR_PLLR_MUL_SHIFT 16
265 #define CKGR_PLLR_MUL_MASK (0x7ff << CKGR_PLLR_MUL_SHIFT) ///< PLL Multiplier mask
266 #define CKGR_PLLR_MUL(value) (CKGR_PLLR_MUL_MASK & ((value) << CKGR_PLLR_MUL_SHIFT))
267 #define CKGR_PLLR_STUCKTO1 29
271 * Defines for bit fields in PMC_MCKR register.
274 #define PMC_MCKR_CSS_MASK 0x3 ///< Master Clock Source Selection mask
275 #define PMC_MCKR_CSS_SLOW_CLK 0x0 ///< Slow Clock is selected
276 #define PMC_MCKR_CSS_MAIN_CLK 0x1 ///< Main Clock is selected
277 #define PMC_MCKR_CSS_PLL_CLK 0x2 ///< PLL Clock is selected
278 #define PMC_MCKR_PRES_SHIFT 4
279 #define PMC_MCKR_PRES_MASK (0x7 << PMC_MCKR_PRES_SHIFT) ///< Processor Clock Prescaler mask
280 #define PMC_MCKR_PRES_CLK (0x0 << PMC_MCKR_PRES_SHIFT) ///< Selected clock
281 #define PMC_MCKR_PRES_CLK_2 (0x1 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 2
282 #define PMC_MCKR_PRES_CLK_4 (0x2 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 4
283 #define PMC_MCKR_PRES_CLK_8 (0x3 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 8
284 #define PMC_MCKR_PRES_CLK_16 (0x4 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 16
285 #define PMC_MCKR_PRES_CLK_32 (0x5 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 32
286 #define PMC_MCKR_PRES_CLK_64 (0x6 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 64
287 #define PMC_MCKR_PRES_CLK_3 (0x7 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 3
288 #define PMC_MCKR_PLLDIV2 12 ///< PLL Divisor by 2
292 * Defines for bit fields in PMC_PCK[3] register.
295 #define PMC_PCK_CSS_MASK 0x7 ///< Master Clock Source Selection mask
296 #define PMC_PCK_CSS_SLOW 0x0 ///< Slow Clock is selected
297 #define PMC_PCK_CSS_MAIN 0x1 ///< Main Clock is selected
298 #define PMC_PCK_CSS_PLL 0x2 ///< PLL Clock is selected
299 #define PMC_PCK_CSS_MCK 0x4 ///< Master Clock is selected
300 #define PMC_PCK_PRES_SHIFT 4
301 #define PMC_PCK_PRES_MASK (0x7 << PMC_PCK_PRES_SHIFT) ///< Programmable Clock Prescaler
302 #define PMC_PCK_PRES_CLK (0x0 << PMC_PCK_PRES_SHIFT) ///< Selected clock
303 #define PMC_PCK_PRES_CLK_2 (0x1 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 2
304 #define PMC_PCK_PRES_CLK_4 (0x2 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 4
305 #define PMC_PCK_PRES_CLK_8 (0x3 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 8
306 #define PMC_PCK_PRES_CLK_16 (0x4 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 16
307 #define PMC_PCK_PRES_CLK_32 (0x5 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 32
308 #define PMC_PCK_PRES_CLK_64 (0x6 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 64
312 * Defines for bit fields in PMC_IER register.
315 #define PMC_IER_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Enable
316 #define PMC_IER_LOCK 1 ///< PLL Lock Interrupt Enable
317 #define PMC_IER_MCKRDY 3 ///< Master Clock Ready Interrupt Enable
318 #define PMC_IER_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Enable
319 #define PMC_IER_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Enable
320 #define PMC_IER_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Enable
321 #define PMC_IER_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Enable
322 #define PMC_IER_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Enable
323 #define PMC_IER_CFDEV 18 ///< Clock Failure Detector Event Interrupt Enable
327 * Defines for bit fields in PMC_IDR register.
330 #define PMC_IDR_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Disable
331 #define PMC_IDR_LOCK 1 ///< PLL Lock Interrupt Disable
332 #define PMC_IDR_MCKRDY 3 ///< Master Clock Ready Interrupt Disable
333 #define PMC_IDR_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Disable
334 #define PMC_IDR_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Disable
335 #define PMC_IDR_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Disable
336 #define PMC_IDR_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Disable
337 #define PMC_IDR_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Disable
338 #define PMC_IDR_CFDEV 18 ///< Clock Failure Detector Event Interrupt Disable
342 * Defines for bit fields in PMC_SR register.
345 #define PMC_SR_MOSCXTS 0 ///< Main XTAL Oscillator Status
346 #define PMC_SR_LOCK 1 ///< PLL Lock Status
347 #define PMC_SR_MCKRDY 3 ///< Master Clock Status
348 #define PMC_SR_OSCSELS 7 ///< Slow Clock Oscillator Selection
349 #define PMC_SR_PCKRDY0 8 ///< Programmable Clock Ready Status
350 #define PMC_SR_PCKRDY1 9 ///< Programmable Clock Ready Status
351 #define PMC_SR_PCKRDY2 10 ///< Programmable Clock Ready Status
352 #define PMC_SR_MOSCSELS 16 ///< Main Oscillator Selection Status
353 #define PMC_SR_MOSCRCS 17 ///< Main On-Chip RC Oscillator Status
354 #define PMC_SR_CFDEV 18 ///< Clock Failure Detector Event
355 #define PMC_SR_CFDS 19 ///< Clock Failure Detector Status
356 #define PMC_SR_FOS 20 ///< Clock Failure Detector Fault Output Status
360 * Defines for bit fields in PMC_IMR register.
363 #define PMC_IMR_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Mask
364 #define PMC_IMR_LOCK 1 ///< PLL Lock Interrupt Mask
365 #define PMC_IMR_MCKRDY 3 ///< Master Clock Ready Interrupt Mask
366 #define PMC_IMR_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Mask
367 #define PMC_IMR_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Mask
368 #define PMC_IMR_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Mask
369 #define PMC_IMR_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Mask
370 #define PMC_IMR_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Mask
371 #define PMC_IMR_CFDEV 18 ///< Clock Failure Detector Event Interrupt Mask
375 * Defines for bit fields in PMC_FSMR register.
378 #define PMC_FSMR_FSTT0 0 ///< Fast Startup Input Enable 0
379 #define PMC_FSMR_FSTT1 1 ///< Fast Startup Input Enable 1
380 #define PMC_FSMR_FSTT2 2 ///< Fast Startup Input Enable 2
381 #define PMC_FSMR_FSTT3 3 ///< Fast Startup Input Enable 3
382 #define PMC_FSMR_FSTT4 4 ///< Fast Startup Input Enable 4
383 #define PMC_FSMR_FSTT5 5 ///< Fast Startup Input Enable 5
384 #define PMC_FSMR_FSTT6 6 ///< Fast Startup Input Enable 6
385 #define PMC_FSMR_FSTT7 7 ///< Fast Startup Input Enable 7
386 #define PMC_FSMR_FSTT8 8 ///< Fast Startup Input Enable 8
387 #define PMC_FSMR_FSTT9 9 ///< Fast Startup Input Enable 9
388 #define PMC_FSMR_FSTT10 10 ///< Fast Startup Input Enable 10
389 #define PMC_FSMR_FSTT11 11 ///< Fast Startup Input Enable 11
390 #define PMC_FSMR_FSTT12 12 ///< Fast Startup Input Enable 12
391 #define PMC_FSMR_FSTT13 13 ///< Fast Startup Input Enable 13
392 #define PMC_FSMR_FSTT14 14 ///< Fast Startup Input Enable 14
393 #define PMC_FSMR_FSTT15 15 ///< Fast Startup Input Enable 15
394 #define PMC_FSMR_RTTAL 16 ///< RTT Alarm Enable
395 #define PMC_FSMR_RTCAL 17 ///< RTC Alarm Enable
396 #define PMC_FSMR_LPM 20 ///< Low Power Mode
400 * Defines for bit fields in PMC_FSPR register.
403 #define PMC_FSPR_FSTP0 0 ///< Fast Startup Input Polarityx
404 #define PMC_FSPR_FSTP1 1 ///< Fast Startup Input Polarityx
405 #define PMC_FSPR_FSTP2 2 ///< Fast Startup Input Polarityx
406 #define PMC_FSPR_FSTP3 3 ///< Fast Startup Input Polarityx
407 #define PMC_FSPR_FSTP4 4 ///< Fast Startup Input Polarityx
408 #define PMC_FSPR_FSTP5 5 ///< Fast Startup Input Polarityx
409 #define PMC_FSPR_FSTP6 6 ///< Fast Startup Input Polarityx
410 #define PMC_FSPR_FSTP7 7 ///< Fast Startup Input Polarityx
411 #define PMC_FSPR_FSTP8 8 ///< Fast Startup Input Polarityx
412 #define PMC_FSPR_FSTP9 9 ///< Fast Startup Input Polarityx
413 #define PMC_FSPR_FSTP10 10 ///< Fast Startup Input Polarityx
414 #define PMC_FSPR_FSTP11 11 ///< Fast Startup Input Polarityx
415 #define PMC_FSPR_FSTP12 12 ///< Fast Startup Input Polarityx
416 #define PMC_FSPR_FSTP13 13 ///< Fast Startup Input Polarityx
417 #define PMC_FSPR_FSTP14 14 ///< Fast Startup Input Polarityx
418 #define PMC_FSPR_FSTP15 15 ///< Fast Startup Input Polarityx
422 * Defines for bit fields in PMC_FOCR register.
425 #define PMC_FOCR_FOCLR 0 ///< Fault Output Clear
429 * Defines for bit fields in PMC_WPMR register.
432 #define PMC_WPMR_WPEN 0 ///< Write Protect Enable
433 #define PMC_WPMR_WPKEY_SHIFT 8
434 #define PMC_WPMR_WPKEY_MASK (0xffffff << PMC_WPMR_WPKEY_SHIFT) ///< Write Protect key mask
435 #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_MASK & ((value) << PMC_WPMR_WPKEY_SHIFT)))
439 * Defines for bit fields in PMC_WPSR register.
442 #define PMC_WPSR_WPVS 0 ///< Write Protect Violation Status
443 #define PMC_WPSR_WPVSRC_SHIFT 8
444 #define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) ///< Write Protect Violation Source mask
448 * Defines for bit fields in PMC_OCR register.
451 #define PMC_OCR_CAL4_MASK 0x7f ///< RC Oscillator Calibration bits for 4 MHz mask
452 #define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_MASK & (value))
453 #define PMC_OCR_SEL4 7 ///< Selection of RC Oscillator Calibration bits for 4 MHz
454 #define PMC_OCR_CAL8_SHIFT 8
455 #define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT) ///< RC Oscillator Calibration bits for 8 MHz mask
456 #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_MASK & ((value) << PMC_OCR_CAL8_SHIFT)))
457 #define PMC_OCR_SEL8 15 ///< Selection of RC Oscillator Calibration bits for 8 MHz
458 #define PMC_OCR_CAL12_SHIFT 16
459 #define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT) ///< RC Oscillator Calibration bits for 12 MHz mask
460 #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_MASK & ((value) << PMC_OCR_CAL12_SHIFT)))
461 #define PMC_OCR_SEL12 23 ///< Selection of RC Oscillator Calibration bits for 12 MHz
465 #endif /* SAM3_PMC_H */