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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief SAM3 PMC hardware.
39 /** PMC registers base. */
40 #define PMC_BASE 0x400E0400
43 * PMC register offsets.
46 #define PMC_SCER_OFF 0x00 ///< System Clock Enable Register
47 #define PMC_SCDR_OFF 0x04 ///< System Clock Disable Register
48 #define PMC_SCSR_OFF 0x08 ///< System Clock Status Register
49 #define PMC_PCER_OFF 0x10 ///< Peripheral Clock Enable Register
50 #define PMC_PCDR_OFF 0x14 ///< Peripheral Clock Disable Register
51 #define PMC_PCSR_OFF 0x18 ///< Peripheral Clock Status Register
52 #define PMC_MOR_OFF 0x20 ///< Main Oscillator Register
53 #define PMC_MCFR_OFF 0x24 ///< Main Clock Frequency Register
54 #define PMC_PLLR_OFF 0x28 ///< PLL Register
55 #define PMC_MCKR_OFF 0x30 ///< Master Clock Register
56 #define PMC_PCK_OFF 0x40 ///< Programmable Clock 0 Register
57 #define PMC_IER_OFF 0x60 ///< Interrupt Enable Register
58 #define PMC_IDR_OFF 0x64 ///< Interrupt Disable Register
59 #define PMC_SR_OFF 0x68 ///< Status Register
60 #define PMC_IMR_OFF 0x6C ///< Interrupt Mask Register
61 #define PMC_FSMR_OFF 0x70 ///< Fast Startup Mode Register
62 #define PMC_FSPR_OFF 0x74 ///< Fast Startup Polarity Register
63 #define PMC_FOCR_OFF 0x78 ///< Fault Output Clear Register
64 #define PMC_WPMR_OFF 0xE4 ///< Write Protect Mode Register
65 #define PMC_WPSR_OFF 0xE8 ///< Write Protect Status Register
66 #define PMC_OCR_OFF 0x110 ///< Oscillator Calibration Register
73 #define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System Clock Enable Register
74 #define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System Clock Disable Register
75 #define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System Clock Status Register
76 #define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral Clock Enable Register
77 #define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral Clock Disable Register
78 #define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral Clock Status Register
79 #define CKGR_MOR (*((reg32_t *)(PMC_BASE + PMC_MOR_OFF ))) ///< Main Oscillator Register
80 #define CKGR_MCFR (*((reg32_t *)(PMC_BASE + PMC_MCFR_OFF))) ///< Main Clock Frequency Register
81 #define CKGR_PLLR (*((reg32_t *)(PMC_BASE + PMC_PLLR_OFF))) ///< PLL Register
82 #define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master Clock Register
83 #define PMC_PCK (*((reg32_t *)(PMC_BASE + PMC_PCK_OFF ))) ///< Programmable Clock 0 Register
84 #define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF ))) ///< Interrupt Enable Register
85 #define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF ))) ///< Interrupt Disable Register
86 #define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF ))) ///< Status Register
87 #define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF ))) ///< Interrupt Mask Register
88 #define PMC_FSMR (*((reg32_t *)(PMC_BASE + PMC_FSMR_OFF))) ///< Fast Startup Mode Register
89 #define PMC_FSPR (*((reg32_t *)(PMC_BASE + PMC_FSPR_OFF))) ///< Fast Startup Polarity Register
90 #define PMC_FOCR (*((reg32_t *)(PMC_BASE + PMC_FOCR_OFF))) ///< Fault Output Clear Register
91 #define PMC_WPMR (*((reg32_t *)(PMC_BASE + PMC_WPMR_OFF))) ///< Write Protect Mode Register
92 #define PMC_WPSR (*((reg32_t *)(PMC_BASE + PMC_WPSR_OFF))) ///< Write Protect Status Register
93 #define PMC_OCR (*((reg32_t *)(PMC_BASE + PMC_OCR_OFF ))) ///< Oscillator Calibration Register
97 * Defines for bit fields in PMC_SCER register.
100 #define PMC_SCER_PCK0 8 ///< Programmable Clock 0 Output Enable
101 #define PMC_SCER_PCK1 9 ///< Programmable Clock 1 Output Enable
102 #define PMC_SCER_PCK2 10 ///< Programmable Clock 2 Output Enable
106 * Defines for bit fields in PMC_SCDR register.
109 #define PMC_SCDR_PCK0 8 ///< Programmable Clock 0 Output Disable
110 #define PMC_SCDR_PCK1 9 ///< Programmable Clock 1 Output Disable
111 #define PMC_SCDR_PCK2 10 ///< Programmable Clock 2 Output Disable
115 * Defines for bit fields in PMC_SCSR register.
118 #define PMC_SCSR_PCK0 8 ///< Programmable Clock 0 Output Status
119 #define PMC_SCSR_PCK1 9 ///< Programmable Clock 1 Output Status
120 #define PMC_SCSR_PCK2 10 ///< Programmable Clock 2 Output Status
124 * Defines for bit fields in PMC_PCER register.
127 #define PMC_PCER_PID2 2 ///< Peripheral Clock 2 Enable
128 #define PMC_PCER_PID3 3 ///< Peripheral Clock 3 Enable
129 #define PMC_PCER_PID4 4 ///< Peripheral Clock 4 Enable
130 #define PMC_PCER_PID5 5 ///< Peripheral Clock 5 Enable
131 #define PMC_PCER_PID6 6 ///< Peripheral Clock 6 Enable
132 #define PMC_PCER_PID7 7 ///< Peripheral Clock 7 Enable
133 #define PMC_PCER_PID8 8 ///< Peripheral Clock 8 Enable
134 #define PMC_PCER_PID9 9 ///< Peripheral Clock 9 Enable
135 #define PMC_PCER_PID10 10 ///< Peripheral Clock 10 Enable
136 #define PMC_PCER_PID11 11 ///< Peripheral Clock 11 Enable
137 #define PMC_PCER_PID12 12 ///< Peripheral Clock 12 Enable
138 #define PMC_PCER_PID13 13 ///< Peripheral Clock 13 Enable
139 #define PMC_PCER_PID14 14 ///< Peripheral Clock 14 Enable
140 #define PMC_PCER_PID15 15 ///< Peripheral Clock 15 Enable
141 #define PMC_PCER_PID16 16 ///< Peripheral Clock 16 Enable
142 #define PMC_PCER_PID17 17 ///< Peripheral Clock 17 Enable
143 #define PMC_PCER_PID18 18 ///< Peripheral Clock 18 Enable
144 #define PMC_PCER_PID19 19 ///< Peripheral Clock 19 Enable
145 #define PMC_PCER_PID20 20 ///< Peripheral Clock 20 Enable
146 #define PMC_PCER_PID21 21 ///< Peripheral Clock 21 Enable
147 #define PMC_PCER_PID22 22 ///< Peripheral Clock 22 Enable
148 #define PMC_PCER_PID23 23 ///< Peripheral Clock 23 Enable
149 #define PMC_PCER_PID24 24 ///< Peripheral Clock 24 Enable
150 #define PMC_PCER_PID25 25 ///< Peripheral Clock 25 Enable
151 #define PMC_PCER_PID26 26 ///< Peripheral Clock 26 Enable
152 #define PMC_PCER_PID27 27 ///< Peripheral Clock 27 Enable
153 #define PMC_PCER_PID28 28 ///< Peripheral Clock 28 Enable
154 #define PMC_PCER_PID29 29 ///< Peripheral Clock 29 Enable
155 #define PMC_PCER_PID30 30 ///< Peripheral Clock 30 Enable
156 #define PMC_PCER_PID31 31 ///< Peripheral Clock 31 Enable
160 * Defines for bit fields in PMC_PCDR register.
163 #define PMC_PCDR_PID2 2 ///< Peripheral Clock 2 Disable
164 #define PMC_PCDR_PID3 3 ///< Peripheral Clock 3 Disable
165 #define PMC_PCDR_PID4 4 ///< Peripheral Clock 4 Disable
166 #define PMC_PCDR_PID5 5 ///< Peripheral Clock 5 Disable
167 #define PMC_PCDR_PID6 6 ///< Peripheral Clock 6 Disable
168 #define PMC_PCDR_PID7 7 ///< Peripheral Clock 7 Disable
169 #define PMC_PCDR_PID8 8 ///< Peripheral Clock 8 Disable
170 #define PMC_PCDR_PID9 9 ///< Peripheral Clock 9 Disable
171 #define PMC_PCDR_PID10 10 ///< Peripheral Clock 10 Disable
172 #define PMC_PCDR_PID11 11 ///< Peripheral Clock 11 Disable
173 #define PMC_PCDR_PID12 12 ///< Peripheral Clock 12 Disable
174 #define PMC_PCDR_PID13 13 ///< Peripheral Clock 13 Disable
175 #define PMC_PCDR_PID14 14 ///< Peripheral Clock 14 Disable
176 #define PMC_PCDR_PID15 15 ///< Peripheral Clock 15 Disable
177 #define PMC_PCDR_PID16 16 ///< Peripheral Clock 16 Disable
178 #define PMC_PCDR_PID17 17 ///< Peripheral Clock 17 Disable
179 #define PMC_PCDR_PID18 18 ///< Peripheral Clock 18 Disable
180 #define PMC_PCDR_PID19 19 ///< Peripheral Clock 19 Disable
181 #define PMC_PCDR_PID20 20 ///< Peripheral Clock 20 Disable
182 #define PMC_PCDR_PID21 21 ///< Peripheral Clock 21 Disable
183 #define PMC_PCDR_PID22 22 ///< Peripheral Clock 22 Disable
184 #define PMC_PCDR_PID23 23 ///< Peripheral Clock 23 Disable
185 #define PMC_PCDR_PID24 24 ///< Peripheral Clock 24 Disable
186 #define PMC_PCDR_PID25 25 ///< Peripheral Clock 25 Disable
187 #define PMC_PCDR_PID26 26 ///< Peripheral Clock 26 Disable
188 #define PMC_PCDR_PID27 27 ///< Peripheral Clock 27 Disable
189 #define PMC_PCDR_PID28 28 ///< Peripheral Clock 28 Disable
190 #define PMC_PCDR_PID29 29 ///< Peripheral Clock 29 Disable
191 #define PMC_PCDR_PID30 30 ///< Peripheral Clock 30 Disable
192 #define PMC_PCDR_PID31 31 ///< Peripheral Clock 31 Disable
196 * Defines for bit fields in PMC_PCSR register.
199 #define PMC_PCSR_PID2 2 ///< Peripheral Clock 2 Status
200 #define PMC_PCSR_PID3 3 ///< Peripheral Clock 3 Status
201 #define PMC_PCSR_PID4 4 ///< Peripheral Clock 4 Status
202 #define PMC_PCSR_PID5 5 ///< Peripheral Clock 5 Status
203 #define PMC_PCSR_PID6 6 ///< Peripheral Clock 6 Status
204 #define PMC_PCSR_PID7 7 ///< Peripheral Clock 7 Status
205 #define PMC_PCSR_PID8 8 ///< Peripheral Clock 8 Status
206 #define PMC_PCSR_PID9 9 ///< Peripheral Clock 9 Status
207 #define PMC_PCSR_PID10 10 ///< Peripheral Clock 10 Status
208 #define PMC_PCSR_PID11 11 ///< Peripheral Clock 11 Status
209 #define PMC_PCSR_PID12 12 ///< Peripheral Clock 12 Status
210 #define PMC_PCSR_PID13 13 ///< Peripheral Clock 13 Status
211 #define PMC_PCSR_PID14 14 ///< Peripheral Clock 14 Status
212 #define PMC_PCSR_PID15 15 ///< Peripheral Clock 15 Status
213 #define PMC_PCSR_PID16 16 ///< Peripheral Clock 16 Status
214 #define PMC_PCSR_PID17 17 ///< Peripheral Clock 17 Status
215 #define PMC_PCSR_PID18 18 ///< Peripheral Clock 18 Status
216 #define PMC_PCSR_PID19 19 ///< Peripheral Clock 19 Status
217 #define PMC_PCSR_PID20 20 ///< Peripheral Clock 20 Status
218 #define PMC_PCSR_PID21 21 ///< Peripheral Clock 21 Status
219 #define PMC_PCSR_PID22 22 ///< Peripheral Clock 22 Status
220 #define PMC_PCSR_PID23 23 ///< Peripheral Clock 23 Status
221 #define PMC_PCSR_PID24 24 ///< Peripheral Clock 24 Status
222 #define PMC_PCSR_PID25 25 ///< Peripheral Clock 25 Status
223 #define PMC_PCSR_PID26 26 ///< Peripheral Clock 26 Status
224 #define PMC_PCSR_PID27 27 ///< Peripheral Clock 27 Status
225 #define PMC_PCSR_PID28 28 ///< Peripheral Clock 28 Status
226 #define PMC_PCSR_PID29 29 ///< Peripheral Clock 29 Status
227 #define PMC_PCSR_PID30 30 ///< Peripheral Clock 30 Status
228 #define PMC_PCSR_PID31 31 ///< Peripheral Clock 31 Status
232 * Defines for bit fields in CKGR_MOR register.
235 #define CKGR_MOR_MOSCXTEN 0 ///< Main Crystal Oscillator Enable
236 #define CKGR_MOR_MOSCXTBY 1 ///< Main Crystal Oscillator Bypass
237 #define CKGR_MOR_WAITMODE 2 ///< Wait Mode Command
238 #define CKGR_MOR_MOSCRCEN 3 ///< Main On-Chip RC Oscillator Enable
239 #define CKGR_MOR_MOSCRCF_SHIFT 4
240 #define CKGR_MOR_MOSCRCF_MASK (0x7 << CKGR_MOR_MOSCRCF_SHIFT) ///< Main On-Chip RC Oscillator Frequency Selection
241 #define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))
242 #define CKGR_MOR_MOSCRCF_4MHZ (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
243 #define CKGR_MOR_MOSCRCF_8MHZ (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
244 #define CKGR_MOR_MOSCRCF_12MHZ (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
245 #define CKGR_MOR_MOSCXTST_SHIFT 8
246 #define CKGR_MOR_MOSCXTST_MASK (0xff << CKGR_MOR_MOSCXTST_SHIFT) ///< Main Crystal Oscillator Start-up Time
247 #define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))
248 #define CKGR_MOR_KEY_SHIFT 16
249 #define CKGR_MOR_KEY_MASK (0xffu << CKGR_MOR_KEY_SHIFT) ///< Password
250 #define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_MASK & ((value) << CKGR_MOR_KEY_SHIFT)))
251 #define CKGR_MOR_MOSCSEL 24 ///< Main Oscillator Selection
252 #define CKGR_MOR_CFDEN 25 ///< Clock Failure Detector Enable
256 * Defines for bit fields in CKGR_MCFR register.
259 #define CKGR_MCFR_MAINF_MASK 0xffff ///< Main Clock Frequency mask
260 #define CKGR_MCFR_MAINFRDY 16 ///< Main Clock Ready
264 * Defines for bit fields in CKGR_PLLR register.
267 #define CKGR_PLLR_DIV_MASK 0xff ///< Divider mask
268 #define CKGR_PLLR_DIV(value) (CKGR_PLLR_DIV_MASK & (value))
269 #define CKGR_PLLR_PLLCOUNT_SHIFT 8
270 #define CKGR_PLLR_PLLCOUNT_MASK (0x3f << CKGR_PLLR_PLLCOUNT_SHIFT) ///< PLL Counter mask
271 #define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_MASK & ((value) << CKGR_PLLR_PLLCOUNT_SHIFT))
272 #define CKGR_PLLR_MUL_SHIFT 16
273 #define CKGR_PLLR_MUL_MASK (0x7ff << CKGR_PLLR_MUL_SHIFT) ///< PLL Multiplier mask
274 #define CKGR_PLLR_MUL(value) (CKGR_PLLR_MUL_MASK & ((value) << CKGR_PLLR_MUL_SHIFT))
275 #define CKGR_PLLR_STUCKTO1 29
279 * Defines for bit fields in PMC_MCKR register.
282 #define PMC_MCKR_CSS_MASK 0x3 ///< Master Clock Source Selection mask
283 #define PMC_MCKR_CSS_SLOW_CLK 0x0 ///< Slow Clock is selected
284 #define PMC_MCKR_CSS_MAIN_CLK 0x1 ///< Main Clock is selected
285 #define PMC_MCKR_CSS_PLL_CLK 0x2 ///< PLL Clock is selected
286 #define PMC_MCKR_PRES_SHIFT 4
287 #define PMC_MCKR_PRES_MASK (0x7 << PMC_MCKR_PRES_SHIFT) ///< Processor Clock Prescaler mask
288 #define PMC_MCKR_PRES_CLK (0x0 << PMC_MCKR_PRES_SHIFT) ///< Selected clock
289 #define PMC_MCKR_PRES_CLK_2 (0x1 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 2
290 #define PMC_MCKR_PRES_CLK_4 (0x2 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 4
291 #define PMC_MCKR_PRES_CLK_8 (0x3 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 8
292 #define PMC_MCKR_PRES_CLK_16 (0x4 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 16
293 #define PMC_MCKR_PRES_CLK_32 (0x5 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 32
294 #define PMC_MCKR_PRES_CLK_64 (0x6 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 64
295 #define PMC_MCKR_PRES_CLK_3 (0x7 << PMC_MCKR_PRES_SHIFT) ///< Selected clock divided by 3
296 #define PMC_MCKR_PLLDIV2 12 ///< PLL Divisor by 2
300 * Defines for bit fields in PMC_PCK[3] register.
303 #define PMC_PCK_CSS_MASK 0x7 ///< Master Clock Source Selection mask
304 #define PMC_PCK_CSS_SLOW 0x0 ///< Slow Clock is selected
305 #define PMC_PCK_CSS_MAIN 0x1 ///< Main Clock is selected
306 #define PMC_PCK_CSS_PLL 0x2 ///< PLL Clock is selected
307 #define PMC_PCK_CSS_MCK 0x4 ///< Master Clock is selected
308 #define PMC_PCK_PRES_SHIFT 4
309 #define PMC_PCK_PRES_MASK (0x7 << PMC_PCK_PRES_SHIFT) ///< Programmable Clock Prescaler
310 #define PMC_PCK_PRES_CLK (0x0 << PMC_PCK_PRES_SHIFT) ///< Selected clock
311 #define PMC_PCK_PRES_CLK_2 (0x1 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 2
312 #define PMC_PCK_PRES_CLK_4 (0x2 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 4
313 #define PMC_PCK_PRES_CLK_8 (0x3 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 8
314 #define PMC_PCK_PRES_CLK_16 (0x4 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 16
315 #define PMC_PCK_PRES_CLK_32 (0x5 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 32
316 #define PMC_PCK_PRES_CLK_64 (0x6 << PMC_PCK_PRES_SHIFT) ///< Selected clock divided by 64
320 * Defines for bit fields in PMC_IER register.
323 #define PMC_IER_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Enable
324 #define PMC_IER_LOCK 1 ///< PLL Lock Interrupt Enable
325 #define PMC_IER_MCKRDY 3 ///< Master Clock Ready Interrupt Enable
326 #define PMC_IER_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Enable
327 #define PMC_IER_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Enable
328 #define PMC_IER_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Enable
329 #define PMC_IER_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Enable
330 #define PMC_IER_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Enable
331 #define PMC_IER_CFDEV 18 ///< Clock Failure Detector Event Interrupt Enable
335 * Defines for bit fields in PMC_IDR register.
338 #define PMC_IDR_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Disable
339 #define PMC_IDR_LOCK 1 ///< PLL Lock Interrupt Disable
340 #define PMC_IDR_MCKRDY 3 ///< Master Clock Ready Interrupt Disable
341 #define PMC_IDR_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Disable
342 #define PMC_IDR_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Disable
343 #define PMC_IDR_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Disable
344 #define PMC_IDR_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Disable
345 #define PMC_IDR_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Disable
346 #define PMC_IDR_CFDEV 18 ///< Clock Failure Detector Event Interrupt Disable
350 * Defines for bit fields in PMC_SR register.
353 #define PMC_SR_MOSCXTS 0 ///< Main XTAL Oscillator Status
354 #define PMC_SR_LOCK 1 ///< PLL Lock Status
355 #define PMC_SR_MCKRDY 3 ///< Master Clock Status
356 #define PMC_SR_OSCSELS 7 ///< Slow Clock Oscillator Selection
357 #define PMC_SR_PCKRDY0 8 ///< Programmable Clock Ready Status
358 #define PMC_SR_PCKRDY1 9 ///< Programmable Clock Ready Status
359 #define PMC_SR_PCKRDY2 10 ///< Programmable Clock Ready Status
360 #define PMC_SR_MOSCSELS 16 ///< Main Oscillator Selection Status
361 #define PMC_SR_MOSCRCS 17 ///< Main On-Chip RC Oscillator Status
362 #define PMC_SR_CFDEV 18 ///< Clock Failure Detector Event
363 #define PMC_SR_CFDS 19 ///< Clock Failure Detector Status
364 #define PMC_SR_FOS 20 ///< Clock Failure Detector Fault Output Status
368 * Defines for bit fields in PMC_IMR register.
371 #define PMC_IMR_MOSCXTS 0 ///< Main Crystal Oscillator Status Interrupt Mask
372 #define PMC_IMR_LOCK 1 ///< PLL Lock Interrupt Mask
373 #define PMC_IMR_MCKRDY 3 ///< Master Clock Ready Interrupt Mask
374 #define PMC_IMR_PCKRDY0 8 ///< Programmable Clock Ready 0 Interrupt Mask
375 #define PMC_IMR_PCKRDY1 9 ///< Programmable Clock Ready 1 Interrupt Mask
376 #define PMC_IMR_PCKRDY2 10 ///< Programmable Clock Ready 2 Interrupt Mask
377 #define PMC_IMR_MOSCSELS 16 ///< Main Oscillator Selection Status Interrupt Mask
378 #define PMC_IMR_MOSCRCS 17 ///< Main On-Chip RC Status Interrupt Mask
379 #define PMC_IMR_CFDEV 18 ///< Clock Failure Detector Event Interrupt Mask
383 * Defines for bit fields in PMC_FSMR register.
386 #define PMC_FSMR_FSTT0 0 ///< Fast Startup Input Enable 0
387 #define PMC_FSMR_FSTT1 1 ///< Fast Startup Input Enable 1
388 #define PMC_FSMR_FSTT2 2 ///< Fast Startup Input Enable 2
389 #define PMC_FSMR_FSTT3 3 ///< Fast Startup Input Enable 3
390 #define PMC_FSMR_FSTT4 4 ///< Fast Startup Input Enable 4
391 #define PMC_FSMR_FSTT5 5 ///< Fast Startup Input Enable 5
392 #define PMC_FSMR_FSTT6 6 ///< Fast Startup Input Enable 6
393 #define PMC_FSMR_FSTT7 7 ///< Fast Startup Input Enable 7
394 #define PMC_FSMR_FSTT8 8 ///< Fast Startup Input Enable 8
395 #define PMC_FSMR_FSTT9 9 ///< Fast Startup Input Enable 9
396 #define PMC_FSMR_FSTT10 10 ///< Fast Startup Input Enable 10
397 #define PMC_FSMR_FSTT11 11 ///< Fast Startup Input Enable 11
398 #define PMC_FSMR_FSTT12 12 ///< Fast Startup Input Enable 12
399 #define PMC_FSMR_FSTT13 13 ///< Fast Startup Input Enable 13
400 #define PMC_FSMR_FSTT14 14 ///< Fast Startup Input Enable 14
401 #define PMC_FSMR_FSTT15 15 ///< Fast Startup Input Enable 15
402 #define PMC_FSMR_RTTAL 16 ///< RTT Alarm Enable
403 #define PMC_FSMR_RTCAL 17 ///< RTC Alarm Enable
404 #define PMC_FSMR_LPM 20 ///< Low Power Mode
408 * Defines for bit fields in PMC_FSPR register.
411 #define PMC_FSPR_FSTP0 0 ///< Fast Startup Input Polarityx
412 #define PMC_FSPR_FSTP1 1 ///< Fast Startup Input Polarityx
413 #define PMC_FSPR_FSTP2 2 ///< Fast Startup Input Polarityx
414 #define PMC_FSPR_FSTP3 3 ///< Fast Startup Input Polarityx
415 #define PMC_FSPR_FSTP4 4 ///< Fast Startup Input Polarityx
416 #define PMC_FSPR_FSTP5 5 ///< Fast Startup Input Polarityx
417 #define PMC_FSPR_FSTP6 6 ///< Fast Startup Input Polarityx
418 #define PMC_FSPR_FSTP7 7 ///< Fast Startup Input Polarityx
419 #define PMC_FSPR_FSTP8 8 ///< Fast Startup Input Polarityx
420 #define PMC_FSPR_FSTP9 9 ///< Fast Startup Input Polarityx
421 #define PMC_FSPR_FSTP10 10 ///< Fast Startup Input Polarityx
422 #define PMC_FSPR_FSTP11 11 ///< Fast Startup Input Polarityx
423 #define PMC_FSPR_FSTP12 12 ///< Fast Startup Input Polarityx
424 #define PMC_FSPR_FSTP13 13 ///< Fast Startup Input Polarityx
425 #define PMC_FSPR_FSTP14 14 ///< Fast Startup Input Polarityx
426 #define PMC_FSPR_FSTP15 15 ///< Fast Startup Input Polarityx
430 * Defines for bit fields in PMC_FOCR register.
433 #define PMC_FOCR_FOCLR 0 ///< Fault Output Clear
437 * Defines for bit fields in PMC_WPMR register.
440 #define PMC_WPMR_WPEN 0 ///< Write Protect Enable
441 #define PMC_WPMR_WPKEY_SHIFT 8
442 #define PMC_WPMR_WPKEY_MASK (0xffffff << PMC_WPMR_WPKEY_SHIFT) ///< Write Protect key mask
443 #define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_MASK & ((value) << PMC_WPMR_WPKEY_SHIFT)))
447 * Defines for bit fields in PMC_WPSR register.
450 #define PMC_WPSR_WPVS 0 ///< Write Protect Violation Status
451 #define PMC_WPSR_WPVSRC_SHIFT 8
452 #define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT) ///< Write Protect Violation Source mask
456 * Defines for bit fields in PMC_OCR register.
459 #define PMC_OCR_CAL4_MASK 0x7f ///< RC Oscillator Calibration bits for 4 MHz mask
460 #define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_MASK & (value))
461 #define PMC_OCR_SEL4 7 ///< Selection of RC Oscillator Calibration bits for 4 MHz
462 #define PMC_OCR_CAL8_SHIFT 8
463 #define PMC_OCR_CAL8_MASK (0x7f << PMC_OCR_CAL8_SHIFT) ///< RC Oscillator Calibration bits for 8 MHz mask
464 #define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_MASK & ((value) << PMC_OCR_CAL8_SHIFT)))
465 #define PMC_OCR_SEL8 15 ///< Selection of RC Oscillator Calibration bits for 8 MHz
466 #define PMC_OCR_CAL12_SHIFT 16
467 #define PMC_OCR_CAL12_MASK (0x7f << PMC_OCR_CAL12_SHIFT) ///< RC Oscillator Calibration bits for 12 MHz mask
468 #define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_MASK & ((value) << PMC_OCR_CAL12_SHIFT)))
469 #define PMC_OCR_SEL12 23 ///< Selection of RC Oscillator Calibration bits for 12 MHz
473 #endif /* SAM3_PMC_H */