4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief SAM3 TWI definitions.
39 /** I2C registers base. */
41 #define TWI0_BASE 0x4008C000
42 #define TWI1_BASE 0x40090000
43 #elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
44 #define TWI0_BASE 0x40018000
45 #define TWI1_BASE 0x4001C000
47 #define TWI0_BASE 0x40084000
48 #define TWI1_BASE 0x40088000
50 #error TWI registers not defined for selected CPU
55 * TWI register offsets.
58 #define TWI_CR_OFF 0x000
59 #define TWI_MMR_OFF 0x004
60 #define TWI_SMR_OFF 0x008
61 #define TWI_IADR_OFF 0x00C
62 #define TWI_CWGR_OFF 0x010
63 #define TWI_SR_OFF 0x020
64 #define TWI_IER_OFF 0x024
65 #define TWI_IDR_OFF 0x028
66 #define TWI_IMR_OFF 0x02C
67 #define TWI_RHR_OFF 0x030
68 #define TWI_THR_OFF 0x034
69 #define TWI_RPR_OFF 0x100
70 #define TWI_RCR_OFF 0x104
71 #define TWI_TPR_OFF 0x108
72 #define TWI_TCR_OFF 0x10C
73 #define TWI_RNPR_OFF 0x110
74 #define TWI_RNCR_OFF 0x114
75 #define TWI_TNPR_OFF 0x118
76 #define TWI_TNCR_OFF 0x11C
77 #define TWI_PTCR_OFF 0x120
78 #define TWI_PTSR_OFF 0x124
86 #define TWI_CR (HWREG(TWI_BASE + TWI_CR_OFF))
87 #define TWI_MMR (HWREG(TWI_BASE + TWI_MMR_OFF))
88 #define TWI_SMR (HWREG(TWI_BASE + TWI_SMR_OFF))
89 #define TWI_IADR (HWREG(TWI_BASE + TWI_IADR_OFF))
90 #define TWI_CWGR (HWREG(TWI_BASE + TWI_CWGR_OFF))
91 #define TWI_SR (HWREG(TWI_BASE + TWI_SR_OFF))
92 #define TWI_IER (HWREG(TWI_BASE + TWI_IER_OFF))
93 #define TWI_IDR (HWREG(TWI_BASE + TWI_IDR_OFF))
94 #define TWI_IMR (HWREG(TWI_BASE + TWI_IMR_OFF))
95 #define TWI_RHR (HWREG(TWI_BASE + TWI_RHR_OFF))
96 #define TWI_THR (HWREG(TWI_BASE + TWI_THR_OFF))
97 #define TWI_RPR (HWREG(TWI_BASE + TWI_RPR_OFF))
98 #define TWI_RCR (HWREG(TWI_BASE + TWI_RCR_OFF))
99 #define TWI_TPR (HWREG(TWI_BASE + TWI_TPR_OFF))
100 #define TWI_TCR (HWREG(TWI_BASE + TWI_TCR_OFF))
101 #define TWI_RNPR (HWREG(TWI_BASE + TWI_RNPR_OFF))
102 #define TWI_RNCR (HWREG(TWI_BASE + TWI_RNCR_OFF))
103 #define TWI_TNPR (HWREG(TWI_BASE + TWI_TNPR_OFF))
104 #define TWI_TNCR (HWREG(TWI_BASE + TWI_TNCR_OFF))
105 #define TWI_PTCR (HWREG(TWI_BASE + TWI_PTCR_OFF))
106 #define TWI_PTSR (HWREG(TWI_BASE + TWI_PTSR_OFF))
110 #define TWI0_CR (HWREG(TWI0_BASE + TWI_CR_OFF))
111 #define TWI0_MMR (HWREG(TWI0_BASE + TWI_MMR_OFF))
112 #define TWI0_SMR (HWREG(TWI0_BASE + TWI_SMR_OFF))
113 #define TWI0_IADR (HWREG(TWI0_BASE + TWI_IADR_OFF))
114 #define TWI0_CWGR (HWREG(TWI0_BASE + TWI_CWGR_OFF))
115 #define TWI0_SR (HWREG(TWI0_BASE + TWI_SR_OFF))
116 #define TWI0_IER (HWREG(TWI0_BASE + TWI_IER_OFF))
117 #define TWI0_IDR (HWREG(TWI0_BASE + TWI_IDR_OFF))
118 #define TWI0_IMR (HWREG(TWI0_BASE + TWI_IMR_OFF))
119 #define TWI0_RHR (HWREG(TWI0_BASE + TWI_RHR_OFF))
120 #define TWI0_THR (HWREG(TWI0_BASE + TWI_THR_OFF))
121 #define TWI0_RPR (HWREG(TWI0_BASE + TWI_RPR_OFF))
122 #define TWI0_RCR (HWREG(TWI0_BASE + TWI_RCR_OFF))
123 #define TWI0_TPR (HWREG(TWI0_BASE + TWI_TPR_OFF))
124 #define TWI0_TCR (HWREG(TWI0_BASE + TWI_TCR_OFF))
125 #define TWI0_RNPR (HWREG(TWI0_BASE + TWI_RNPR_OFF))
126 #define TWI0_RNCR (HWREG(TWI0_BASE + TWI_RNCR_OFF))
127 #define TWI0_TNPR (HWREG(TWI0_BASE + TWI_TNPR_OFF))
128 #define TWI0_TNCR (HWREG(TWI0_BASE + TWI_TNCR_OFF))
129 #define TWI0_PTCR (HWREG(TWI0_BASE + TWI_PTCR_OFF))
130 #define TWI0_PTSR (HWREG(TWI0_BASE + TWI_PTSR_OFF))
134 #define TWI1_CR (HWREG(TWI1_BASE + TWI_CR_OFF))
135 #define TWI1_MMR (HWREG(TWI1_BASE + TWI_MMR_OFF))
136 #define TWI1_SMR (HWREG(TWI1_BASE + TWI_SMR_OFF))
137 #define TWI1_IADR (HWREG(TWI1_BASE + TWI_IADR_OFF))
138 #define TWI1_CWGR (HWREG(TWI1_BASE + TWI_CWGR_OFF))
139 #define TWI1_SR (HWREG(TWI1_BASE + TWI_SR_OFF))
140 #define TWI1_IER (HWREG(TWI1_BASE + TWI_IER_OFF))
141 #define TWI1_IDR (HWREG(TWI1_BASE + TWI_IDR_OFF))
142 #define TWI1_IMR (HWREG(TWI1_BASE + TWI_IMR_OFF))
143 #define TWI1_RHR (HWREG(TWI1_BASE + TWI_RHR_OFF))
144 #define TWI1_THR (HWREG(TWI1_BASE + TWI_THR_OFF))
145 #define TWI1_RPR (HWREG(TWI1_BASE + TWI_RPR_OFF))
146 #define TWI1_RCR (HWREG(TWI1_BASE + TWI_RCR_OFF))
147 #define TWI1_TPR (HWREG(TWI1_BASE + TWI_TPR_OFF))
148 #define TWI1_TCR (HWREG(TWI1_BASE + TWI_TCR_OFF))
149 #define TWI1_RNPR (HWREG(TWI1_BASE + TWI_RNPR_OFF))
150 #define TWI1_RNCR (HWREG(TWI1_BASE + TWI_RNCR_OFF))
151 #define TWI1_TNPR (HWREG(TWI1_BASE + TWI_TNPR_OFF))
152 #define TWI1_TNCR (HWREG(TWI1_BASE + TWI_TNCR_OFF))
153 #define TWI1_PTCR (HWREG(TWI1_BASE + TWI_PTCR_OFF))
154 #define TWI1_PTSR (HWREG(TWI1_BASE + TWI_PTSR_OFF))
160 * TWI_CR: (TWI Offset: 0x00) Control Register
163 #define TWI_CR_START BV(0)
164 #define TWI_CR_STOP BV(1)
165 #define TWI_CR_MSEN BV(2)
166 #define TWI_CR_MSDIS BV(3)
167 #define TWI_CR_SVEN BV(4)
168 #define TWI_CR_SVDIS BV(5)
169 #define TWI_CR_QUICK BV(6)
170 #define TWI_CR_SWRST BV(7)
174 * TWI_MMR: (TWI Offset: 0x04) Master Mode Register
177 #define TWI_MMR_IADRSZ_SHIFT 8
178 #define TWI_MMR_IADRSZ_MASK (0x3 << TWI_MMR_IADRSZ_SHIFT)
179 #define TWI_MMR_IADRSZ_NONE (0x0 << 8)
180 #define TWI_MMR_IADRSZ_1_BYTE BV(8)
181 #define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8)
182 #define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8)
183 #define TWI_MMR_MREAD BV(12)
184 #define TWI_MMR_DADR_SHIFT 16
185 #define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
186 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_MASK & ((value) << TWI_MMR_DADR_SHIFT)))
190 * TWI_SMR: (TWI Offset: 0x08) Slave Mode Register
193 #define TWI_SMR_SADR_SHIFT 16
194 #define TWI_SMR_SADR_MASK (0x7f << TWI_SMR_SADR_SHIFT)
195 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_MASK & ((value) << TWI_SMR_SADR_SHIFT)))
199 * TWI_IADR: (TWI Offset: 0x0C) Internal Address Register
202 #define TWI_IADR_IADR_SHIFT 0
203 #define TWI_IADR_IADR_MASK (0xffffff << TWI_IADR_IADR_SHIFT)
204 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_MASK & ((value) << TWI_IADR_IADR_SHIFT)))
208 * TWI_CWGR: (TWI Offset: 0x10) Clock Waveform Generator Register
211 #define TWI_CWGR_CLDIV_SHIFT 0
212 #define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
213 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_MASK & ((value) << TWI_CWGR_CLDIV_SHIFT)))
214 #define TWI_CWGR_CHDIV_SHIFT 8
215 #define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CHDIV_SHIFT)
216 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_MASK & ((value) << TWI_CWGR_CHDIV_SHIFT)))
217 #define TWI_CWGR_CKDIV_SHIFT 16
218 #define TWI_CWGR_CKDIV_MASK (0x7 << TWI_CWGR_CKDIV_SHIFT)
219 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_MASK & ((value) << TWI_CWGR_CKDIV_SHIFT)))
223 * TWI_SR: (TWI Offset: 0x20) Status Register
226 #define TWI_SR_TXCOMP BV(0)
227 #define TWI_SR_RXRDY BV(1)
228 #define TWI_SR_TXRDY BV(2)
229 #define TWI_SR_SVREAD BV(3)
230 #define TWI_SR_SVACC BV(4)
231 #define TWI_SR_GACC BV(5)
232 #define TWI_SR_OVRE BV(6)
233 #define TWI_SR_NACK BV(8)
234 #define TWI_SR_ARBLST BV(9)
235 #define TWI_SR_SCLWS BV(10)
236 #define TWI_SR_EOSACC BV(11)
237 #define TWI_SR_ENDRX BV(12)
238 #define TWI_SR_ENDTX BV(13)
239 #define TWI_SR_RXBUFF BV(14)
240 #define TWI_SR_TXBUFE BV(15)
244 * TWI_IER: (TWI Offset: 0x24) Interrupt Enable Register
247 #define TWI_IER_TXCOMP BV(0)
248 #define TWI_IER_RXRDY BV(1)
249 #define TWI_IER_TXRDY BV(2)
250 #define TWI_IER_SVACC BV(4)
251 #define TWI_IER_GACC BV(5)
252 #define TWI_IER_OVRE BV(6)
253 #define TWI_IER_NACK BV(8)
254 #define TWI_IER_ARBLST BV(9)
255 #define TWI_IER_SCL_WS BV(10)
256 #define TWI_IER_EOSACC BV(11)
257 #define TWI_IER_ENDRX BV(12)
258 #define TWI_IER_ENDTX BV(13)
259 #define TWI_IER_RXBUFF BV(14)
260 #define TWI_IER_TXBUFE BV(15)
264 * TWI_IDR: (TWI Offset: 0x28) Interrupt Disable Register
267 #define TWI_IDR_TXCOMP BV(0)
268 #define TWI_IDR_RXRDY BV(1)
269 #define TWI_IDR_TXRDY BV(2)
270 #define TWI_IDR_SVACC BV(4)
271 #define TWI_IDR_GACC BV(5)
272 #define TWI_IDR_OVRE BV(6)
273 #define TWI_IDR_NACK BV(8)
274 #define TWI_IDR_ARBLST BV(9)
275 #define TWI_IDR_SCL_WS BV(10)
276 #define TWI_IDR_EOSACC BV(11)
277 #define TWI_IDR_ENDRX BV(12)
278 #define TWI_IDR_ENDTX BV(13)
279 #define TWI_IDR_RXBUFF BV(14)
280 #define TWI_IDR_TXBUFE BV(15)
284 * TWI_IMR: (TWI Offset: 0x2C) Interrupt Mask Register
287 #define TWI_IMR_TXCOMP BV(0)
288 #define TWI_IMR_RXRDY BV(1)
289 #define TWI_IMR_TXRDY BV(2)
290 #define TWI_IMR_SVACC BV(4)
291 #define TWI_IMR_GACC BV(5)
292 #define TWI_IMR_OVRE BV(6)
293 #define TWI_IMR_NACK BV(8)
294 #define TWI_IMR_ARBLST BV(9)
295 #define TWI_IMR_SCL_WS BV(10)
296 #define TWI_IMR_EOSACC BV(11)
297 #define TWI_IMR_ENDRX BV(12)
298 #define TWI_IMR_ENDTX BV(13)
299 #define TWI_IMR_RXBUFF BV(14)
300 #define TWI_IMR_TXBUFE BV(15)
304 * TWI_RHR: (TWI Offset: 0x30) Receive Holding Register
307 #define TWI_RHR_RXDATA_SHIFT 0
308 #define TWI_RHR_RXDATA_MASK (0xff << TWI_RHR_RXDATA_SHIFT)
312 * TWI_THR: (TWI Offset: 0x34) Transmit Holding Register
315 #define TWI_THR_TXDATA_SHIFT 0
316 #define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
317 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_MASK & ((value) << TWI_THR_TXDATA_SHIFT)))
321 * TWI_RPR: (TWI Offset: 0x100) Receive Pointer Register
324 #define TWI_RPR_RXPTR_SHIFT 0
325 #define TWI_RPR_RXPTR_MASK (0xffffffff << TWI_RPR_RXPTR_SHIFT)
326 #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_MASK & ((value) << TWI_RPR_RXPTR_SHIFT)))
330 * TWI_RCR: (TWI Offset: 0x104) Receive Counter Register
333 #define TWI_RCR_RXCTR_SHIFT 0
334 #define TWI_RCR_RXCTR_MASK (0xffff << TWI_RCR_RXCTR_SHIFT)
335 #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_MASK & ((value) << TWI_RCR_RXCTR_SHIFT)))
339 * TWI_TPR: (TWI Offset: 0x108) Transmit Pointer Register
342 #define TWI_TPR_TXPTR_SHIFT 0
343 #define TWI_TPR_TXPTR_MASK (0xffffffff << TWI_TPR_TXPTR_SHIFT)
344 #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_MASK & ((value) << TWI_TPR_TXPTR_SHIFT)))
348 * TWI_TCR: (TWI Offset: 0x10C) Transmit Counter Register
351 #define TWI_TCR_TXCTR_SHIFT 0
352 #define TWI_TCR_TXCTR_MASK (0xffff << TWI_TCR_TXCTR_SHIFT)
353 #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_MASK & ((value) << TWI_TCR_TXCTR_SHIFT)))
357 * TWI_RNPR: (TWI Offset: 0x110) Receive Next Pointer Register
360 #define TWI_RNPR_RXNPTR_SHIFT 0
361 #define TWI_RNPR_RXNPTR_MASK (0xffffffff << TWI_RNPR_RXNPTR_SHIFT)
362 #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_MASK & ((value) << TWI_RNPR_RXNPTR_SHIFT)))
366 * TWI_RNCR: (TWI Offset: 0x114) Receive Next Counter Register
369 #define TWI_RNCR_RXNCTR_SHIFT 0
370 #define TWI_RNCR_RXNCTR_MASK (0xffff << TWI_RNCR_RXNCTR_SHIFT)
371 #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_MASK & ((value) << TWI_RNCR_RXNCTR_SHIFT)))
375 * TWI_TNPR: (TWI Offset: 0x118) Transmit Next Pointer Register
378 #define TWI_TNPR_TXNPTR_SHIFT 0
379 #define TWI_TNPR_TXNPTR_MASK (0xffffffff << TWI_TNPR_TXNPTR_SHIFT)
380 #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_MASK & ((value) << TWI_TNPR_TXNPTR_SHIFT)))
384 * TWI_TNCR: (TWI Offset: 0x11C) Transmit Next Counter Register
387 #define TWI_TNCR_TXNCTR_SHIFT 0
388 #define TWI_TNCR_TXNCTR_MASK (0xffff << TWI_TNCR_TXNCTR_SHIFT)
389 #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_MASK & ((value) << TWI_TNCR_TXNCTR_SHIFT)))
393 * TWI_PTCR: (TWI Offset: 0x120) Transfer Control Register
396 #define TWI_PTCR_RXTEN BV(0)
397 #define TWI_PTCR_RXTDIS BV(1)
398 #define TWI_PTCR_TXTEN BV(8)
399 #define TWI_PTCR_TXTDIS BV(9)
403 * TWI_PTSR: (TWI Offset: 0x124) Transfer Status Register
406 #define TWI_PTSR_RXTEN BV(0)
407 #define TWI_PTSR_TXTEN BV(8)
410 #endif /* SAM3_TWI_H */