4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \version $Id: ser_at91.c 20881 2008-03-04 14:07:02Z batt $
38 * \author Daniele Basile <asterix@develer.com>
41 #include "hw_ser.h" /* Required for bus macros overrides */
42 #include "hw_cpu.h" /* CLOCK_FREQ */
44 #include <cfg/debug.h>
46 #include <appconfig.h>
53 #include <drv/ser_p.h>
55 #include <mware/fifobuf.h>
58 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
61 * \name Overridable serial bus hooks
63 * These can be redefined in hw.h to implement
64 * special bus policies such as half-duplex, 485, etc.
68 * TXBEGIN TXCHAR TXEND TXOFF
69 * | __________|__________ | |
72 * ______ __ __ __ __ __ __ ________________
73 * \/ \/ \/ \/ \/ \/ \/
74 * ______/\__/\__/\__/\__/\__/\__/
81 #ifndef SER_UART0_BUS_TXINIT
83 * Default TXINIT macro - invoked in uart0_init()
85 * - Disable GPIO on USART0 tx/rx pins
87 #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128
88 #warning Check USART0 pins!
90 #define SER_UART0_BUS_TXINIT do { \
91 PIOA_PDR = BV(RXD0) | BV(TXD0); \
96 #ifndef SER_UART0_BUS_TXBEGIN
98 * Invoked before starting a transmission
100 #define SER_UART0_BUS_TXBEGIN
103 #ifndef SER_UART0_BUS_TXCHAR
105 * Invoked to send one character.
107 #define SER_UART0_BUS_TXCHAR(c) do { \
112 #ifndef SER_UART0_BUS_TXEND
114 * Invoked as soon as the txfifo becomes empty
116 #define SER_UART0_BUS_TXEND
119 /* End USART0 macros */
121 #ifndef SER_UART1_BUS_TXINIT
123 * Default TXINIT macro - invoked in uart1_init()
125 * - Disable GPIO on USART1 tx/rx pins
127 #if !CPU_ARM_AT91SAM7S256 && !CPU_ARM_AT91SAM7X256 && !CPU_ARM_AT91SAM7X128
128 #warning Check USART1 pins!
130 #define SER_UART1_BUS_TXINIT do { \
131 PIOA_PDR = BV(RXD1) | BV(TXD1); \
136 #ifndef SER_UART1_BUS_TXBEGIN
138 * Invoked before starting a transmission
140 #define SER_UART1_BUS_TXBEGIN
143 #ifndef SER_UART1_BUS_TXCHAR
145 * Invoked to send one character.
147 #define SER_UART1_BUS_TXCHAR(c) do { \
152 #ifndef SER_UART1_BUS_TXEND
154 * Invoked as soon as the txfifo becomes empty
156 #define SER_UART1_BUS_TXEND
160 * \name Overridable SPI hooks
162 * These can be redefined in hw.h to implement
163 * special bus policies such as slave select pin handling, etc.
168 #ifndef SER_SPI0_BUS_TXINIT
170 * Default TXINIT macro - invoked in spi_init()
171 * The default is no action.
173 #define SER_SPI0_BUS_TXINIT
176 #ifndef SER_SPI0_BUS_TXCLOSE
178 * Invoked after the last character has been transmitted.
179 * The default is no action.
181 #define SER_SPI0_BUS_TXCLOSE
184 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
186 #ifndef SER_SPI1_BUS_TXINIT
188 * Default TXINIT macro - invoked in spi_init()
189 * The default is no action.
191 #define SER_SPI1_BUS_TXINIT
194 #ifndef SER_SPI1_BUS_TXCLOSE
196 * Invoked after the last character has been transmitted.
197 * The default is no action.
199 #define SER_SPI1_BUS_TXCLOSE
206 * \def CONFIG_SER_STROBE
208 * This is a debug facility that can be used to
209 * monitor SER interrupt activity on an external pin.
211 * To use strobes, redefine the macros SER_STROBE_ON,
212 * SER_STROBE_OFF and SER_STROBE_INIT and set
213 * CONFIG_SER_STROBE to 1.
215 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
216 #define SER_STROBE_ON do {/*nop*/} while(0)
217 #define SER_STROBE_OFF do {/*nop*/} while(0)
218 #define SER_STROBE_INIT do {/*nop*/} while(0)
222 /* From the high-level serial driver */
223 extern struct Serial ser_handles[SER_CNT];
225 /* TX and RX buffers */
226 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
227 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
229 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
230 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
232 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
233 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
234 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
235 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
236 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
240 * Internal hardware state structure
242 * The \a sending variable is true while the transmission
243 * interrupt is retriggering itself.
245 * For the USARTs the \a sending flag is useful for taking specific
246 * actions before sending a burst of data, at the start of a trasmission
247 * but not before every char sent.
249 * For the SPI, this flag is necessary because the SPI sends and receives
250 * bytes at the same time and the SPI IRQ is unique for send/receive.
251 * The only way to start transmission is to write data in SPDR (this
252 * is done by spi_starttx()). We do this *only* if a transfer is
253 * not already started.
257 struct SerialHardware hw;
258 volatile bool sending;
263 * These are to trick GCC into *not* using absolute addressing mode
264 * when accessing ser_handles, which is very expensive.
266 * Accessing through these pointers generates much shorter
267 * (and hopefully faster) code.
269 struct Serial *ser_uart0 = &ser_handles[SER_UART0];
270 struct Serial *ser_uart1 = &ser_handles[SER_UART1];
272 struct Serial *ser_spi0 = &ser_handles[SER_SPI0];
273 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
274 struct Serial *ser_spi1 = &ser_handles[SER_SPI1];
277 static void uart0_irq_dispatcher(void);
278 static void uart1_irq_dispatcher(void);
279 static void spi0_irq_handler(void);
280 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
281 static void spi1_irq_handler(void);
284 * Callbacks for USART0
286 static void uart0_init(
287 UNUSED_ARG(struct SerialHardware *, _hw),
288 UNUSED_ARG(struct Serial *, ser))
290 US0_IDR = 0xFFFFFFFF;
291 /* Set the vector. */
292 AIC_SVR(US0_ID) = uart0_irq_dispatcher;
293 /* Initialize to level sensitive with defined priority. */
294 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
295 PMC_PCER = BV(US0_ID);
299 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
300 * - Enable both the receiver and the transmitter
301 * - Enable only the RX complete interrupt
303 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
304 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
305 US0_CR = BV(US_RXEN) | BV(US_TXEN);
306 US0_IER = BV(US_RXRDY);
308 SER_UART0_BUS_TXINIT;
310 /* Enable the USART IRQ */
311 AIC_IECR = BV(US0_ID);
316 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
318 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
321 static void uart0_enabletxirq(struct SerialHardware *_hw)
323 struct ArmSerial *hw = (struct ArmSerial *)_hw;
326 * WARNING: racy code here! The tx interrupt sets hw->sending to false
327 * when it runs with an empty fifo. The order of statements in the
334 * - Enable the transmitter
335 * - Enable TX empty interrupt
337 SER_UART0_BUS_TXBEGIN;
338 US0_IER = BV(US_TXEMPTY);
342 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
344 /* Compute baud-rate period */
345 US0_BRGR = CLOCK_FREQ / (16 * rate);
346 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
349 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
351 US0_MR &= ~US_PAR_MASK;
352 /* Set UART parity */
355 case SER_PARITY_NONE:
361 case SER_PARITY_EVEN:
364 US0_MR |= US_PAR_EVEN;
370 US0_MR |= US_PAR_ODD;
379 * Callbacks for USART1
381 static void uart1_init(
382 UNUSED_ARG(struct SerialHardware *, _hw),
383 UNUSED_ARG(struct Serial *, ser))
385 US1_IDR = 0xFFFFFFFF;
386 /* Set the vector. */
387 AIC_SVR(US1_ID) = uart1_irq_dispatcher;
388 /* Initialize to level sensitive with defined priority. */
389 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
390 PMC_PCER = BV(US1_ID);
394 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
395 * - Enable both the receiver and the transmitter
396 * - Enable only the RX complete interrupt
398 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
399 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
400 US1_CR = BV(US_RXEN) | BV(US_TXEN);
401 US1_IER = BV(US_RXRDY);
403 SER_UART1_BUS_TXINIT;
405 /* Enable the USART IRQ */
406 AIC_IECR = BV(US1_ID);
411 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
413 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
416 static void uart1_enabletxirq(struct SerialHardware *_hw)
418 struct ArmSerial *hw = (struct ArmSerial *)_hw;
421 * WARNING: racy code here! The tx interrupt sets hw->sending to false
422 * when it runs with an empty fifo. The order of statements in the
429 * - Enable the transmitter
430 * - Enable TX empty interrupt
432 SER_UART1_BUS_TXBEGIN;
433 US1_IER = BV(US_TXEMPTY);
437 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
439 /* Compute baud-rate period */
440 US1_BRGR = CLOCK_FREQ / (16 * rate);
441 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
444 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
446 US1_MR &= ~US_PAR_MASK;
447 /* Set UART parity */
450 case SER_PARITY_NONE:
456 case SER_PARITY_EVEN:
459 US1_MR |= US_PAR_EVEN;
465 US1_MR |= US_PAR_ODD;
475 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
477 /* Disable PIO on SPI pins */
478 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
481 SPI0_CR = BV(SPI_SWRST);
484 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
485 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
487 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
491 * At reset clock division factor is set to 0, that is
492 * *forbidden*. Set SPI clock to minimum to keep it valid.
494 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
496 /* Disable all irqs */
497 SPI0_IDR = 0xFFFFFFFF;
498 /* Set the vector. */
499 AIC_SVR(SPI0_ID) = spi0_irq_handler;
500 /* Initialize to edge triggered with defined priority. */
501 AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
502 /* Enable the USART IRQ */
503 AIC_IECR = BV(SPI0_ID);
504 PMC_PCER = BV(SPI0_ID);
506 /* Enable interrupt on tx buffer empty */
507 SPI0_IER = BV(SPI_TXEMPTY);
510 SPI0_CR = BV(SPI_SPIEN);
518 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
521 SPI0_CR = BV(SPI_SPIDIS);
523 /* Disable all irqs */
524 SPI0_IDR = 0xFFFFFFFF;
526 SER_SPI0_BUS_TXCLOSE;
528 /* Enable PIO on SPI pins */
529 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
532 static void spi0_starttx(struct SerialHardware *_hw)
534 struct ArmSerial *hw = (struct ArmSerial *)_hw;
537 IRQ_SAVE_DISABLE(flags);
539 /* Send data only if the SPI is not already transmitting */
540 if (!hw->sending && !fifo_isempty(&ser_spi0->txfifo))
543 SPI0_TDR = fifo_pop(&ser_spi0->txfifo);
549 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
551 SPI0_CSR0 &= ~SPI_SCBR;
553 ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate));
554 SPI0_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT;
557 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
559 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
561 /* Disable PIO on SPI pins */
562 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
565 SPI1_CR = BV(SPI_SWRST);
568 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
569 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
571 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
575 * At reset clock division factor is set to 0, that is
576 * *forbidden*. Set SPI clock to minimum to keep it valid.
578 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
580 /* Disable all irqs */
581 SPI1_IDR = 0xFFFFFFFF;
582 /* Set the vector. */
583 AIC_SVR(SPI1_ID) = spi1_irq_handler;
584 /* Initialize to edge triggered with defined priority. */
585 AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
586 /* Enable the USART IRQ */
587 AIC_IECR = BV(SPI1_ID);
588 PMC_PCER = BV(SPI1_ID);
590 /* Enable interrupt on tx buffer empty */
591 SPI1_IER = BV(SPI_TXEMPTY);
594 SPI1_CR = BV(SPI_SPIEN);
602 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
605 SPI1_CR = BV(SPI_SPIDIS);
607 /* Disable all irqs */
608 SPI1_IDR = 0xFFFFFFFF;
610 SER_SPI1_BUS_TXCLOSE;
612 /* Enable PIO on SPI pins */
613 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
616 static void spi1_starttx(struct SerialHardware *_hw)
618 struct ArmSerial *hw = (struct ArmSerial *)_hw;
621 IRQ_SAVE_DISABLE(flags);
623 /* Send data only if the SPI is not already transmitting */
624 if (!hw->sending && !fifo_isempty(&ser_spi1->txfifo))
627 SPI1_TDR = fifo_pop(&ser_spi1->txfifo);
633 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
635 SPI1_CSR0 &= ~SPI_SCBR;
637 ASSERT((uint8_t)DIV_ROUND(CLOCK_FREQ, rate));
638 SPI1_CSR0 |= DIV_ROUND(CLOCK_FREQ, rate) << SPI_SCBR_SHIFT;
642 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
648 static bool tx_sending(struct SerialHardware* _hw)
650 struct ArmSerial *hw = (struct ArmSerial *)_hw;
654 // FIXME: move into compiler.h? Ditch?
656 #define C99INIT(name,val) .name = val
657 #elif defined(__GNUC__)
658 #define C99INIT(name,val) name: val
660 #warning No designated initializers, double check your code
661 #define C99INIT(name,val) (val)
665 * High-level interface data structures
667 static const struct SerialHardwareVT UART0_VT =
669 C99INIT(init, uart0_init),
670 C99INIT(cleanup, uart0_cleanup),
671 C99INIT(setBaudrate, uart0_setbaudrate),
672 C99INIT(setParity, uart0_setparity),
673 C99INIT(txStart, uart0_enabletxirq),
674 C99INIT(txSending, tx_sending),
677 static const struct SerialHardwareVT UART1_VT =
679 C99INIT(init, uart1_init),
680 C99INIT(cleanup, uart1_cleanup),
681 C99INIT(setBaudrate, uart1_setbaudrate),
682 C99INIT(setParity, uart1_setparity),
683 C99INIT(txStart, uart1_enabletxirq),
684 C99INIT(txSending, tx_sending),
687 static const struct SerialHardwareVT SPI0_VT =
689 C99INIT(init, spi0_init),
690 C99INIT(cleanup, spi0_cleanup),
691 C99INIT(setBaudrate, spi0_setbaudrate),
692 C99INIT(setParity, spi_setparity),
693 C99INIT(txStart, spi0_starttx),
694 C99INIT(txSending, tx_sending),
696 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
697 static const struct SerialHardwareVT SPI1_VT =
699 C99INIT(init, spi1_init),
700 C99INIT(cleanup, spi1_cleanup),
701 C99INIT(setBaudrate, spi1_setbaudrate),
702 C99INIT(setParity, spi_setparity),
703 C99INIT(txStart, spi1_starttx),
704 C99INIT(txSending, tx_sending),
708 static struct ArmSerial UARTDescs[SER_CNT] =
712 C99INIT(table, &UART0_VT),
713 C99INIT(txbuffer, uart0_txbuffer),
714 C99INIT(rxbuffer, uart0_rxbuffer),
715 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
716 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
718 C99INIT(sending, false),
722 C99INIT(table, &UART1_VT),
723 C99INIT(txbuffer, uart1_txbuffer),
724 C99INIT(rxbuffer, uart1_rxbuffer),
725 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
726 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
728 C99INIT(sending, false),
733 C99INIT(table, &SPI0_VT),
734 C99INIT(txbuffer, spi0_txbuffer),
735 C99INIT(rxbuffer, spi0_rxbuffer),
736 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
737 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
739 C99INIT(sending, false),
741 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
744 C99INIT(table, &SPI1_VT),
745 C99INIT(txbuffer, spi1_txbuffer),
746 C99INIT(rxbuffer, spi1_rxbuffer),
747 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
748 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
750 C99INIT(sending, false),
756 struct SerialHardware *ser_hw_getdesc(int unit)
758 ASSERT(unit < SER_CNT);
759 return &UARTDescs[unit].hw;
763 * Serial 0 TX interrupt handler
765 static void uart0_irq_tx(void)
769 struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
771 if (fifo_isempty(txfifo))
774 * - Disable the TX empty interrupts
776 US0_IDR = BV(US_TXEMPTY);
778 UARTDescs[SER_UART0].sending = false;
782 char c = fifo_pop(txfifo);
783 SER_UART0_BUS_TXCHAR(c);
790 * Serial 0 RX complete interrupt handler.
792 static void uart0_irq_rx(void)
796 /* Should be read before US_CRS */
797 ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
798 US0_CR = BV(US_RSTSTA);
801 struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
803 if (fifo_isfull(rxfifo))
804 ser_uart0->status |= SERRF_RXFIFOOVERRUN;
806 fifo_push(rxfifo, c);
812 * Serial IRQ dispatcher for USART0.
814 static void uart0_irq_dispatcher(void) __attribute__ ((interrupt));
815 static void uart0_irq_dispatcher(void)
817 if (US0_CSR & BV(US_RXRDY))
820 if (US0_CSR & BV(US_TXEMPTY))
823 /* Inform hw that we have served the IRQ */
828 * Serial 1 TX interrupt handler
830 static void uart1_irq_tx(void)
834 struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
836 if (fifo_isempty(txfifo))
839 * - Disable the TX empty interrupts
841 US1_IDR = BV(US_TXEMPTY);
843 UARTDescs[SER_UART1].sending = false;
847 char c = fifo_pop(txfifo);
848 SER_UART1_BUS_TXCHAR(c);
855 * Serial 1 RX complete interrupt handler.
857 static void uart1_irq_rx(void)
861 /* Should be read before US_CRS */
862 ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
863 US1_CR = BV(US_RSTSTA);
866 struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
868 if (fifo_isfull(rxfifo))
869 ser_uart1->status |= SERRF_RXFIFOOVERRUN;
871 fifo_push(rxfifo, c);
877 * Serial IRQ dispatcher for USART1.
879 static void uart1_irq_dispatcher(void) __attribute__ ((interrupt));
880 static void uart1_irq_dispatcher(void)
882 if (US1_CSR & BV(US_RXRDY))
885 if (US1_CSR & BV(US_TXEMPTY))
888 /* Inform hw that we have served the IRQ */
893 * SPI0 interrupt handler
895 static void spi0_irq_handler(void) __attribute__ ((interrupt));
896 static void spi0_irq_handler(void)
901 /* Read incoming byte. */
902 if (!fifo_isfull(&ser_spi0->rxfifo))
903 fifo_push(&ser_spi0->rxfifo, c);
907 ser_spi0->status |= SERRF_RXFIFOOVERRUN;
911 if (!fifo_isempty(&ser_spi0->txfifo))
912 SPI0_TDR = fifo_pop(&ser_spi0->txfifo);
914 UARTDescs[SER_SPI0].sending = false;
916 /* Inform hw that we have served the IRQ */
922 #if CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7X256
924 * SPI1 interrupt handler
926 static void spi1_irq_handler(void) __attribute__ ((interrupt));
927 static void spi1_irq_handler(void)
932 /* Read incoming byte. */
933 if (!fifo_isfull(&ser_spi1->rxfifo))
934 fifo_push(&ser_spi1->rxfifo, c);
938 ser_spi1->status |= SERRF_RXFIFOOVERRUN;
942 if (!fifo_isempty(&ser_spi1->txfifo))
943 SPI1_TDR = fifo_pop(&ser_spi1->txfifo);
945 UARTDescs[SER_SPI1].sending = false;
947 /* Inform hw that we have served the IRQ */