4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
37 * \author Daniele Basile <asterix@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
45 #include <cfg/debug.h>
50 #include <drv/irq_cm3.h>
55 #include <drv/ser_p.h>
57 #include <struct/fifobuf.h>
60 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
63 * \name Overridable serial bus hooks
65 * These can be redefined in hw.h to implement
66 * special bus policies such as half-duplex, 485, etc.
70 * TXBEGIN TXCHAR TXEND TXOFF
71 * | __________|__________ | |
74 * ______ __ __ __ __ __ __ ________________
75 * \/ \/ \/ \/ \/ \/ \/
76 * ______/\__/\__/\__/\__/\__/\__/
83 #ifndef SER_UART0_BUS_TXINIT
85 * Default TXINIT macro - invoked in uart0_init()
87 * - Disable GPIO on USART0 tx/rx pins
89 #if CPU_ARM_AT91 && !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
90 #warning Check USART0 pins!
92 #define SER_UART0_BUS_TXINIT do { \
93 PIOA_PDR = BV(RXD0) | BV(TXD0); \
94 PIO_PERIPH_SEL(PIOA_BASE, BV(RXD0) | BV(TXD0), PIO_PERIPH_A); \
98 #ifndef SER_UART0_BUS_TXBEGIN
100 * Invoked before starting a transmission
102 #define SER_UART0_BUS_TXBEGIN
105 #ifndef SER_UART0_BUS_TXCHAR
107 * Invoked to send one character.
109 #define SER_UART0_BUS_TXCHAR(c) do { \
114 #ifndef SER_UART0_BUS_TXEND
116 * Invoked as soon as the txfifo becomes empty
118 #define SER_UART0_BUS_TXEND
121 /* End USART0 macros */
125 #ifndef SER_UART1_BUS_TXINIT
127 * Default TXINIT macro - invoked in uart1_init()
129 * - Disable GPIO on USART1 tx/rx pins
131 #if CPU_ARM_AT91 && !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
132 #warning Check USART1 pins!
134 #define SER_UART1_BUS_TXINIT do { \
135 PIOA_PDR = BV(RXD1) | BV(TXD1); \
136 PIO_PERIPH_SEL(PIOA_BASE, BV(RXD1) | BV(TXD1), PIO_PERIPH_A); \
140 #ifndef SER_UART1_BUS_TXBEGIN
142 * Invoked before starting a transmission
144 #define SER_UART1_BUS_TXBEGIN
147 #ifndef SER_UART1_BUS_TXCHAR
149 * Invoked to send one character.
151 #define SER_UART1_BUS_TXCHAR(c) do { \
156 #ifndef SER_UART1_BUS_TXEND
158 * Invoked as soon as the txfifo becomes empty
160 #define SER_UART1_BUS_TXEND
166 * \name Overridable SPI hooks
168 * These can be redefined in hw.h to implement
169 * special bus policies such as slave select pin handling, etc.
174 #ifndef SER_SPI0_BUS_TXINIT
176 * Default TXINIT macro - invoked in spi_init()
177 * The default is no action.
180 #define SER_SPI0_BUS_TXINIT do { \
181 /* Disable PIO on SPI pins */ \
182 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
183 /* SPI is peripheral A on SAM3X,A,N,S,U */ \
184 PIO_PERIPH_SEL(PIOA_BASE, BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO), PIO_PERIPH_A); \
187 #define SER_SPI0_BUS_TXINIT do { \
188 /* Disable PIO on SPI pins */ \
189 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
194 #ifndef SER_SPI0_BUS_TXCLOSE
196 * Invoked after the last character has been transmitted.
197 * The default is no action.
199 #define SER_SPI0_BUS_TXCLOSE do { \
200 /* Enable PIO on SPI pins */ \
201 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
207 #ifndef SER_SPI1_BUS_TXINIT
209 * Default TXINIT macro - invoked in spi_init()
210 * The default is no action.
212 #define SER_SPI1_BUS_TXINIT do { \
213 /* Disable PIO on SPI pins */ \
214 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
215 /* SPI1 pins are on B peripheral function! */ \
216 PIOA_BSR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
220 #ifndef SER_SPI1_BUS_TXCLOSE
222 * Invoked after the last character has been transmitted.
223 * The default is no action.
225 #define SER_SPI1_BUS_TXCLOSE do { \
226 /* Enable PIO on SPI pins */ \
227 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO); \
235 * \name Core dependent interrupt handling macros
237 * Atmel serial hardware is used on different CPU cores,
238 * i.e. SAM3 and SAM7. The user interface of the serial
239 * subsystem is identical but core interrupt controllers
246 INLINE void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler)
248 /* Set the vector. */
249 AIC_SVR(irq) = uart0_irq_dispatcher;
251 /* Initialize to level/edge sensitive with defined priority. */
253 if (irq == SPI0_ID || irq == SPI1_ID)
257 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_SRCTYPE_MASK) | AIC_SRCTYPE_INT_EDGE_TRIGGERED;
259 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_SRCTYPE_MASK) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE;
265 INLINE void sysirq_setPriority(sysirq_t irq, int prio)
267 AIC_SMR(irq) = (AIC_SMR(irq) & ~AIC_PRIOR_MASK) | SERIRQ_PRIORITY;
270 /** Inform hw that we have served the IRQ */
271 #define SER_INT_ACK do { \
277 /** Inform hw that we have served the IRQ */
278 #define SER_INT_ACK do { /* nop */ } while (0)
281 #error No interrupt handling macros defined for current architecture
286 /* From the high-level serial driver */
287 extern struct Serial *ser_handles[SER_CNT];
289 /* TX and RX buffers */
290 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
291 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
293 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
294 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
296 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
297 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
299 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
300 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
304 * Internal hardware state structure
306 * The \a sending variable is true while the transmission
307 * interrupt is retriggering itself.
309 * For the USARTs the \a sending flag is useful for taking specific
310 * actions before sending a burst of data, at the start of a trasmission
311 * but not before every char sent.
313 * For the SPI, this flag is necessary because the SPI sends and receives
314 * bytes at the same time and the SPI IRQ is unique for send/receive.
315 * The only way to start transmission is to write data in SPDR (this
316 * is done by spi_starttx()). We do this *only* if a transfer is
317 * not already started.
321 struct SerialHardware hw;
322 volatile bool sending;
325 static ISR_PROTO(uart0_irq_dispatcher);
327 static ISR_PROTO(uart1_irq_dispatcher);
329 static ISR_PROTO(spi0_irq_handler);
331 static ISR_PROTO(spi1_irq_handler);
334 * Callbacks for USART0
336 static void uart0_init(
337 UNUSED_ARG(struct SerialHardware *, _hw),
338 UNUSED_ARG(struct Serial *, ser))
340 US0_IDR = 0xFFFFFFFF;
341 PMC_PCER = BV(US0_ID);
345 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
346 * - Enable both the receiver and the transmitter
347 * - Enable only the RX complete interrupt
349 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
350 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
351 US0_CR = BV(US_RXEN) | BV(US_TXEN);
352 US0_IER = BV(US_RXRDY);
354 SER_UART0_BUS_TXINIT;
356 sysirq_setPriority(INT_US0, SERIRQ_PRIORITY);
357 sysirq_setHandler(INT_US0, uart0_irq_dispatcher);
362 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
364 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
367 static void uart0_enabletxirq(struct SerialHardware *_hw)
369 struct ArmSerial *hw = (struct ArmSerial *)_hw;
372 * WARNING: racy code here! The tx interrupt sets hw->sending to false
373 * when it runs with an empty fifo. The order of statements in the
380 * - Enable the transmitter
381 * - Enable TX empty interrupt
383 SER_UART0_BUS_TXBEGIN;
384 US0_IER = BV(US_TXEMPTY);
388 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
390 /* Compute baud-rate period */
391 US0_BRGR = CPU_FREQ / (16 * rate);
392 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
395 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
397 US0_MR &= ~US_PAR_MASK;
398 /* Set UART parity */
401 case SER_PARITY_NONE:
407 case SER_PARITY_EVEN:
410 US0_MR |= US_PAR_EVEN;
416 US0_MR |= US_PAR_ODD;
427 * Callbacks for USART1
429 static void uart1_init(
430 UNUSED_ARG(struct SerialHardware *, _hw),
431 UNUSED_ARG(struct Serial *, ser))
433 US1_IDR = 0xFFFFFFFF;
434 PMC_PCER = BV(US1_ID);
438 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
439 * - Enable both the receiver and the transmitter
440 * - Enable only the RX complete interrupt
442 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
443 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
444 US1_CR = BV(US_RXEN) | BV(US_TXEN);
445 US1_IER = BV(US_RXRDY);
447 SER_UART1_BUS_TXINIT;
449 sysirq_setPriority(INT_US1, SERIRQ_PRIORITY);
450 sysirq_setHandler(INT_US1, uart1_irq_dispatcher);
455 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
457 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
460 static void uart1_enabletxirq(struct SerialHardware *_hw)
462 struct ArmSerial *hw = (struct ArmSerial *)_hw;
465 * WARNING: racy code here! The tx interrupt sets hw->sending to false
466 * when it runs with an empty fifo. The order of statements in the
473 * - Enable the transmitter
474 * - Enable TX empty interrupt
476 SER_UART1_BUS_TXBEGIN;
477 US1_IER = BV(US_TXEMPTY);
481 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
483 /* Compute baud-rate period */
484 US1_BRGR = CPU_FREQ / (16 * rate);
485 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
488 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
490 US1_MR &= ~US_PAR_MASK;
491 /* Set UART parity */
494 case SER_PARITY_NONE:
500 case SER_PARITY_EVEN:
503 US1_MR |= US_PAR_EVEN;
509 US1_MR |= US_PAR_ODD;
517 #endif /* USART_PORTS > 1 */
520 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
525 SPI0_CR = BV(SPI_SWRST);
528 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
529 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
531 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
535 * At reset clock division factor is set to 0, that is
536 * *forbidden*. Set SPI clock to minimum to keep it valid.
537 * Set all possible chip select registers in case user manually
538 * change CPS field in SPI_MR.
540 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
541 SPI0_CSR1 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
542 SPI0_CSR2 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
543 SPI0_CSR3 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
545 /* Disable all irqs */
546 SPI0_IDR = 0xFFFFFFFF;
548 //sysirq_setPriority(INT_SPI0, SERIRQ_PRIORITY);
549 sysirq_setHandler(INT_SPI0, spi0_irq_handler);
550 PMC_PCER = BV(SPI0_ID);
553 SPI0_CR = BV(SPI_SPIEN);
558 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
561 SPI0_CR = BV(SPI_SPIDIS);
563 /* Disable all irqs */
564 SPI0_IDR = 0xFFFFFFFF;
566 SER_SPI0_BUS_TXCLOSE;
569 static void spi0_starttx(struct SerialHardware *_hw)
571 struct ArmSerial *hw = (struct ArmSerial *)_hw;
574 IRQ_SAVE_DISABLE(flags);
576 /* Send data only if the SPI is not already transmitting */
577 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
580 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
581 /* Enable interrupt on tx buffer empty */
582 SPI0_IER = BV(SPI_TXEMPTY);
588 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
590 SPI0_CSR0 &= ~SPI_SCBR;
592 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
593 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
598 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
603 SPI1_CR = BV(SPI_SWRST);
606 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
607 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
609 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
613 * At reset clock division factor is set to 0, that is
614 * *forbidden*. Set SPI clock to minimum to keep it valid.
615 * Set all possible chip select registers in case user manually
616 * change chip select.
618 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
619 SPI1_CSR1 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
620 SPI1_CSR2 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
621 SPI1_CSR3 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
623 /* Disable all SPI irqs */
624 SPI1_IDR = 0xFFFFFFFF;
626 sysirq_setPriority(INT_SPI1, SERIRQ_PRIORITY);
627 sysirq_setHandler(INT_SPI1, spi1_irq_dispatcher);
628 PMC_PCER = BV(SPI1_ID);
631 SPI1_CR = BV(SPI_SPIEN);
636 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
639 SPI1_CR = BV(SPI_SPIDIS);
641 /* Disable all irqs */
642 SPI1_IDR = 0xFFFFFFFF;
644 SER_SPI1_BUS_TXCLOSE;
647 static void spi1_starttx(struct SerialHardware *_hw)
649 struct ArmSerial *hw = (struct ArmSerial *)_hw;
652 IRQ_SAVE_DISABLE(flags);
654 /* Send data only if the SPI is not already transmitting */
655 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
658 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
659 /* Enable interrupt on tx buffer empty */
660 SPI1_IER = BV(SPI_TXEMPTY);
666 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
668 SPI1_CSR0 &= ~SPI_SCBR;
670 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
671 SPI1_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
675 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
681 static bool tx_sending(struct SerialHardware* _hw)
683 struct ArmSerial *hw = (struct ArmSerial *)_hw;
687 // FIXME: move into compiler.h? Ditch?
689 #define C99INIT(name,val) .name = val
690 #elif defined(__GNUC__)
691 #define C99INIT(name,val) name: val
693 #warning No designated initializers, double check your code
694 #define C99INIT(name,val) (val)
698 * High-level interface data structures
700 static const struct SerialHardwareVT UART0_VT =
702 C99INIT(init, uart0_init),
703 C99INIT(cleanup, uart0_cleanup),
704 C99INIT(setBaudrate, uart0_setbaudrate),
705 C99INIT(setParity, uart0_setparity),
706 C99INIT(txStart, uart0_enabletxirq),
707 C99INIT(txSending, tx_sending),
712 static const struct SerialHardwareVT UART1_VT =
714 C99INIT(init, uart1_init),
715 C99INIT(cleanup, uart1_cleanup),
716 C99INIT(setBaudrate, uart1_setbaudrate),
717 C99INIT(setParity, uart1_setparity),
718 C99INIT(txStart, uart1_enabletxirq),
719 C99INIT(txSending, tx_sending),
722 #endif /* USART_PORTS > 1 */
724 static const struct SerialHardwareVT SPI0_VT =
726 C99INIT(init, spi0_init),
727 C99INIT(cleanup, spi0_cleanup),
728 C99INIT(setBaudrate, spi0_setbaudrate),
729 C99INIT(setParity, spi_setparity),
730 C99INIT(txStart, spi0_starttx),
731 C99INIT(txSending, tx_sending),
734 static const struct SerialHardwareVT SPI1_VT =
736 C99INIT(init, spi1_init),
737 C99INIT(cleanup, spi1_cleanup),
738 C99INIT(setBaudrate, spi1_setbaudrate),
739 C99INIT(setParity, spi_setparity),
740 C99INIT(txStart, spi1_starttx),
741 C99INIT(txSending, tx_sending),
745 static struct ArmSerial UARTDescs[SER_CNT] =
749 C99INIT(table, &UART0_VT),
750 C99INIT(txbuffer, uart0_txbuffer),
751 C99INIT(rxbuffer, uart0_rxbuffer),
752 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
753 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
755 C99INIT(sending, false),
760 C99INIT(table, &UART1_VT),
761 C99INIT(txbuffer, uart1_txbuffer),
762 C99INIT(rxbuffer, uart1_rxbuffer),
763 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
764 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
766 C99INIT(sending, false),
772 C99INIT(table, &SPI0_VT),
773 C99INIT(txbuffer, spi0_txbuffer),
774 C99INIT(rxbuffer, spi0_rxbuffer),
775 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
776 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
778 C99INIT(sending, false),
783 C99INIT(table, &SPI1_VT),
784 C99INIT(txbuffer, spi1_txbuffer),
785 C99INIT(rxbuffer, spi1_rxbuffer),
786 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
787 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
789 C99INIT(sending, false),
795 struct SerialHardware *ser_hw_getdesc(int unit)
797 ASSERT(unit < SER_CNT);
798 return &UARTDescs[unit].hw;
802 * Serial 0 TX interrupt handler
804 INLINE void uart0_irq_tx(void)
808 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
810 if (fifo_isempty(txfifo))
813 * - Disable the TX empty interrupts
815 US0_IDR = BV(US_TXEMPTY);
817 UARTDescs[SER_UART0].sending = false;
821 char c = fifo_pop(txfifo);
822 SER_UART0_BUS_TXCHAR(c);
829 * Serial 0 RX complete interrupt handler.
831 INLINE void uart0_irq_rx(void)
835 /* Should be read before US_CRS */
836 ser_handles[SER_UART0]->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
837 US0_CR = BV(US_RSTSTA);
840 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
842 if (fifo_isfull(rxfifo))
843 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
845 fifo_push(rxfifo, c);
851 * Serial IRQ dispatcher for USART0.
853 static DECLARE_ISR(uart0_irq_dispatcher)
855 if (US0_CSR & BV(US_RXRDY))
858 if (US0_CSR & BV(US_TXEMPTY))
867 * Serial 1 TX interrupt handler
869 INLINE void uart1_irq_tx(void)
873 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
875 if (fifo_isempty(txfifo))
878 * - Disable the TX empty interrupts
880 US1_IDR = BV(US_TXEMPTY);
882 UARTDescs[SER_UART1].sending = false;
886 char c = fifo_pop(txfifo);
887 SER_UART1_BUS_TXCHAR(c);
894 * Serial 1 RX complete interrupt handler.
896 INLINE void uart1_irq_rx(void)
900 /* Should be read before US_CRS */
901 ser_handles[SER_UART1]->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
902 US1_CR = BV(US_RSTSTA);
905 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
907 if (fifo_isfull(rxfifo))
908 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
910 fifo_push(rxfifo, c);
916 * Serial IRQ dispatcher for USART1.
918 static DECLARE_ISR(uart1_irq_dispatcher)
920 if (US1_CSR & BV(US_RXRDY))
923 if (US1_CSR & BV(US_TXEMPTY))
929 #endif /* USART_PORTS > 1 */
932 * SPI0 interrupt handler
934 static DECLARE_ISR(spi0_irq_handler)
939 /* Read incoming byte. */
940 if (!fifo_isfull(&ser_handles[SER_SPI0]->rxfifo))
941 fifo_push(&ser_handles[SER_SPI0]->rxfifo, c);
945 ser_handles[SER_SPI0]->status |= SERRF_RXFIFOOVERRUN;
949 if (!fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
950 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
953 UARTDescs[SER_SPI0].sending = false;
954 /* Disable interrupt on tx buffer empty */
955 SPI0_IDR = BV(SPI_TXEMPTY);
966 * SPI1 interrupt handler
968 static DECLARE_ISR(spi1_irq_handler)
973 /* Read incoming byte. */
974 if (!fifo_isfull(&ser_handles[SER_SPI1]->rxfifo))
975 fifo_push(&ser_handles[SER_SPI1]->rxfifo, c);
979 ser_handles[SER_SPI1]->status |= SERRF_RXFIFOOVERRUN;
983 if (!fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
984 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
987 UARTDescs[SER_SPI1].sending = false;
988 /* Disable interrupt on tx buffer empty */
989 SPI1_IDR = BV(SPI_TXEMPTY);