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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief LM3S1968 Synchronous Serial Interface (SSI) driver.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/compiler.h>
39 #include <cfg/debug.h>
41 #include "drv/ssi_lm3s.h"
43 /* SSI clocking informations (CPSDVSR + SCR) */
51 * Evaluate the SSI clock prescale (SSICPSR) and SSI serial clock rate (SCR).
53 INLINE struct ssi_clock
54 lm3s_ssi_prescale(unsigned int bitrate)
58 for (ret.cpsdvsr = 2, ret.scr = CPU_FREQ / bitrate / ret.cpsdvsr - 1;
59 ret.scr > 255; ret.cpsdvsr += 2);
60 ASSERT(ret.cpsdvsr < 255);
66 * Initialize the SSI interface.
68 * @base: the SSI port base address.
69 * @frame: the data transfer protocol (SSI_FRF_MOTO_MODE_0,
70 * SSI_FRF_MOTO_MODE_1, SSI_FRF_MOTO_MODE_2, SSI_FRF_MOTO_MODE_3, SSI_FRF_TI or
72 * @mode: the mode of operation (SSI_MODE_MASTER, SSI_MODE_SLAVE,
74 * @bitrate: the SSI clock rate
75 * @data_width: number of bits per frame
77 * Return 0 in case of success, a negative value otherwise.
79 int lm3s_ssi_init(uint32_t base, uint32_t frame, int mode,
80 unsigned int bitrate, unsigned int data_width)
82 struct ssi_clock ssi_clock;
84 ASSERT(base == SSI0_BASE || base == SSI1_BASE);
85 /* Configure the SSI operating mode */
88 /* SSI Slave Mode Output Disable */
89 case SSI_MODE_SLAVE_OD:
90 HWREG(base + SSI_O_CR1) = SSI_CR1_SOD;
94 HWREG(base + SSI_O_CR1) = SSI_CR1_MS;
98 HWREG(base + SSI_O_CR1) = 0;
104 /* Configure the peripheral clock and frame format */
105 ssi_clock = lm3s_ssi_prescale(bitrate);
106 HWREG(base + SSI_O_CPSR) = ssi_clock.cpsdvsr;
107 HWREG(base + SSI_O_CR0) =
108 (ssi_clock.scr << 8) |
110 (frame & SSI_CR0_FRF_M) |
115 /* Enable the SSI interface */
116 void lm3s_ssi_enable(uint32_t base)
118 HWREG(base + SSI_O_CR1) |= SSI_CR1_SSE;
121 /* Disable the SSI interface */
122 void lm3s_ssi_disable(uint32_t base)
124 HWREG(base + SSI_O_CR1) &= ~SSI_CR1_SSE;
128 * Put a frame into the SSI transmit FIFO.
130 * NOTE: the upper bits of the frame will be automatically discarded by the
131 * hardware according to the frame data width, configured by lm3s_ssi_init().
133 void lm3s_ssi_write_frame(uint32_t base, uint32_t val)
135 /* Wait for available space in the TX FIFO */
136 while (!(HWREG(base + SSI_O_SR) & SSI_SR_TNF))
138 /* Enqueue data to the TX FIFO */
139 HWREG(base + SSI_O_DR) = val;
143 * Put a frame into the SSI transmit FIFO without blocking.
145 * NOTE: the upper bits of the frame will be automatically discarded by the
146 * hardware according to the frame data width, configured by lm3s_ssi_init().
148 * Return the number of frames written to the TX FIFO.
150 int lm3s_ssi_write_frame_nonblocking(uint32_t base, uint32_t val)
152 /* Check for available space in the TX FIFO */
153 if (!(HWREG(base + SSI_O_SR) & SSI_SR_TNF))
155 /* Enqueue data to the TX FIFO */
156 HWREG(base + SSI_O_DR) = val;
161 * Get a frame from the SSI receive FIFO.
163 void lm3s_ssi_read_frame(uint32_t base, uint32_t *val)
165 /* Wait for data available in the RX FIFO */
166 while (!(HWREG(base + SSI_O_SR) & SSI_SR_RNE))
168 /* Read data from SSI RX FIFO */
169 *val = HWREG(base + SSI_O_DR);
173 * Get a frame into the SSI receive FIFO without blocking.
175 * Return the number of frames read from the RX FIFO.
177 int lm3s_ssi_read_frame_nonblocking(uint32_t base, uint32_t *val)
179 /* Check for data available in the RX FIFO */
180 if (!(HWREG(base + SSI_O_SR) & SSI_SR_RNE))
182 /* Read data from SSI RX FIFO */
183 *val = HWREG(base + SSI_O_DR);
188 * Check if the SSI transmitter is busy or not
190 * This allows to determine whether the TX FIFO have been cleared by the
191 * hardware, so the transmission can be safely considered completed.
193 bool lm3s_ssi_txdone(uint32_t base)
195 /* Check if the SSI is busy */
196 return (HWREG(base + SSI_O_SR) & SSI_SR_BSY) ? true : false;