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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32F103xx adc definition.
39 #include <cpu/types.h>
42 #define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
43 #define ADC_MODE_REGINJECSIMULT ((uint32_t)0x00010000)
44 #define ADC_MODE_REGSIMULT_ALTERTRIG ((uint32_t)0x00020000)
45 #define ADC_MODE_INJECSIMULT_FASTINTERL ((uint32_t)0x00030000)
46 #define ADC_MODE_INJECSIMULT_SLOWINTERL ((uint32_t)0x00040000)
47 #define ADC_MODE_INJECSIMULT ((uint32_t)0x00050000)
48 #define ADC_MODE_REGSIMULT ((uint32_t)0x00060000)
49 #define ADC_MODE_FASTINTERL ((uint32_t)0x00070000)
50 #define ADC_MODE_SLOWINTERL ((uint32_t)0x00080000)
51 #define ADC_MODE_ALTERTRIG ((uint32_t)0x00090000)
53 /* ADC extrenal trigger sources for regular channels conversion */
54 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
55 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)0x00020000)
56 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)0x00040000)
57 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)0x00060000)
58 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)0x00080000)
59 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)0x000A0000)
60 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)0x000C0000)
61 #define ADC_EXTERNALTRIGCONV_NONE ((uint32_t)0x000E0000)
64 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
65 #define ADC_DATAALIGN_LEFT ((uint32_t)0x00000800)
68 #define ADC_CHANNEL_0 ((uint8_t)0x00)
69 #define ADC_CHANNEL_1 ((uint8_t)0x01)
70 #define ADC_CHANNEL_2 ((uint8_t)0x02)
71 #define ADC_CHANNEL_3 ((uint8_t)0x03)
72 #define ADC_CHANNEL_4 ((uint8_t)0x04)
73 #define ADC_CHANNEL_5 ((uint8_t)0x05)
74 #define ADC_CHANNEL_6 ((uint8_t)0x06)
75 #define ADC_CHANNEL_7 ((uint8_t)0x07)
76 #define ADC_CHANNEL_8 ((uint8_t)0x08)
77 #define ADC_CHANNEL_9 ((uint8_t)0x09)
78 #define ADC_CHANNEL_10 ((uint8_t)0x0A)
79 #define ADC_CHANNEL_11 ((uint8_t)0x0B)
80 #define ADC_CHANNEL_12 ((uint8_t)0x0C)
81 #define ADC_CHANNEL_13 ((uint8_t)0x0D)
82 #define ADC_CHANNEL_14 ((uint8_t)0x0E)
83 #define ADC_CHANNEL_15 ((uint8_t)0x0F)
84 #define ADC_CHANNEL_16 ((uint8_t)0x10)
85 #define ADC_CHANNEL_17 ((uint8_t)0x11)
87 /* ADC sampling times */
88 #define ADC_SAMPLETIME_1CYCLES5 ((uint8_t)0x00)
89 #define ADC_SAMPLETIME_7CYCLES5 ((uint8_t)0x01)
90 #define ADC_SAMPLETIME_13CYCLES5 ((uint8_t)0x02)
91 #define ADC_SAMPLETIME_28CYCLES5 ((uint8_t)0x03)
92 #define ADC_SAMPLETIME_41CYCLES5 ((uint8_t)0x04)
93 #define ADC_SAMPLETIME_55CYCLES5 ((uint8_t)0x05)
94 #define ADC_SAMPLETIME_71CYCLES5 ((uint8_t)0x06)
95 #define ADC_SAMPLETIME_239CYCLES5 ((uint8_t)0x07)
97 /* ADC extrenal trigger sources for injected channels conversion */
98 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000)
99 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00001000)
100 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)0x00002000)
101 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)0x00003000)
102 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)0x00004000)
103 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)0x00005000)
104 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)0x00006000)
105 #define ADC_EXTERNALTRIGINJECCONV_NONE ((uint32_t)0x00007000)
107 /* ADC injected channel selection */
108 #define ADC_INJECTEDCHANNEL_1 ((uint8_t)0x14)
109 #define ADC_INJECTEDCHANNEL_2 ((uint8_t)0x18)
110 #define ADC_INJECTEDCHANNEL_3 ((uint8_t)0x1C)
111 #define ADC_INJECTEDCHANNEL_4 ((uint8_t)0x20)
113 /* ADC analog watchdog selection */
114 #define ADC_ANALOGWATCHDOG_SINGLEREGENABLE ((uint32_t)0x00800200)
115 #define ADC_ANALOGWATCHDOG_SINGLEINJECENABLE ((uint32_t)0x00400200)
116 #define ADC_ANALOGWATCHDOG_SINGLEREGORINJECENABLE ((uint32_t)0x00C00200)
117 #define ADC_ANALOGWATCHDOG_ALLREGENABLE ((uint32_t)0x00800000)
118 #define ADC_ANALOGWATCHDOG_ALLINJECENABLE ((uint32_t)0x00400000)
119 #define ADC_ANALOGWATCHDOG_ALLREGALLINJECENABLE ((uint32_t)0x00C00000)
120 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
122 /* ADC interrupts definition */
123 #define ADC_IT_EOC ((uint16_t)0x0220)
124 #define ADC_IT_AWD ((uint16_t)0x0140)
125 #define ADC_IT_JEOC ((uint16_t)0x0480)
127 /* ADC flags definition */
128 #define ADC_FLAG_AWD ((uint8_t)0x01)
129 #define ADC_FLAG_EOC ((uint8_t)0x02)
130 #define ADC_FLAG_JEOC ((uint8_t)0x04)
131 #define ADC_FLAG_JSTRT ((uint8_t)0x08)
132 #define ADC_FLAG_STRT ((uint8_t)0X10)
135 /* ADC ADON mask */
\r
136 #define CR2_ADON_SET ((uint32_t)0x00000001)
\r
137 #define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE)
\r
140 #define CR2_DMA_SET ((uint16_t)0x0100)
\r
141 #define CR2_DMA_RESET ((uint16_t)0xFEFF)
\r
143 /* ADC RSTCAL mask */
\r
144 #define CR2_RSTCAL_SET ((uint16_t)0x0008)
\r
147 #define CR2_CAL_SET ((uint16_t)0x0004)
\r
149 /* ADC SWSTRT mask */
\r
150 #define CR2_SWSTRT_SET ((uint32_t)0x00400000)
\r
152 /* ADC DISCNUM mask */
\r
153 #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
\r
155 /* ADC DISCEN mask */
\r
156 #define CR1_DISCEN_SET ((uint32_t)0x00000800)
\r
157 #define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF)
\r
159 /* ADC EXTTRIG mask */
\r
160 #define CR2_EXTTRIG_SET ((uint32_t)0x00100000)
\r
161 #define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF)
\r
163 /* ADC Software start mask */
\r
164 #define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000)
\r
165 #define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF)
\r
167 /* ADC JAUTO mask */
\r
168 #define CR1_JAUTO_SET ((uint32_t)0x00000400)
\r
169 #define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF)
\r
171 /* ADC JDISCEN mask */
\r
172 #define CR1_JDISCEN_SET ((uint32_t)0x00001000)
\r
173 #define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF)
\r
175 /* ADC JEXTSEL mask */
\r
176 #define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF)
\r
178 /* ADC JEXTTRIG mask */
\r
179 #define CR2_JEXTTRIG_SET ((uint32_t)0x00008000)
\r
180 #define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF)
\r
182 /* ADC JSWSTRT mask */
\r
183 #define CR2_JSWSTRT_SET ((uint32_t)0x00200000)
\r
185 /* ADC injected software start mask */
\r
186 #define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000)
\r
187 #define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF)
\r
189 /* ADC AWDCH mask */
\r
190 #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
\r
193 #define SQR3_SQ_MASK ((uint8_t)0x1F)
\r
194 #define SQR2_SQ_MASK ((uint8_t)0x1F)
\r
195 #define SQR1_SQ_MASK ((uint8_t)0x1F)
196 #define SQR1_SQ_LEN_MASK 0xF
197 #define SQR1_SQ_LEN_SHIFT 20
\r
199 /* ADC JSQx mask */
\r
200 #define JSQR_JSQ_SET ((uint8_t)0x1F)
\r
203 #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
\r
205 /* ADC SMPx mask */
\r
206 #define SMPR1_SMP_SET ((uint8_t)0x07)
\r
207 #define SMPR2_SMP_SET ((uint8_t)0x07)
\r
209 /* ADC Analog watchdog enable mode mask */
\r
210 #define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)
\r
212 /* ADC TSPD mask */
\r
213 #define CR2_TSVREFE_SET ((uint32_t)0x00800000)
\r
214 #define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
\r
216 /* ADC JDRx registers= offset */
\r
217 #define JDR_OFFSET ((uint8_t)0x28)
\r
219 /* ADC CR1 register */
226 #define CR1_DISCEN 11
227 #define CR1_JDISCEN 12
228 #define CR1_JAWDEN 22
231 /* ADC CR2 register */
238 #define CR2_JEXTTRIG 15
239 #define CR2_EXTTRIG 20
240 #define CR2_JSWSTART 21
241 #define CR2_SWSTART 22
242 #define CR2_TSVREFE 23
251 /* ADC sample time */
252 #define SMPR1_CH17 21
253 #define SMPR1_CH16 18
254 #define SMPR1_CH15 15
255 #define SMPR1_CH14 12
272 /* ADC registers Masks */
\r
273 #define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF)
\r
274 #define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD)
\r
275 #define SQR1_CLEAR_MASK ((uint32_t)0xFF0FFFFF)
279 /* ADC defines for SMT32F103Bxx */
280 #define ADC_TEMP_V25 4300 // uV / C
281 #define ADC_TEMP_SLOPE 1430 // mV
282 #define ADC_TEMP_CONST 25000
283 #define ADC_TEMP_CH 16
284 #define ADC_VREFINT_CH 17
310 #endif /* STM32_ADC_H */