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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief STM32F103xx I2C definition.
39 #include <cpu/types.h>
43 #define I2C_MODE_I2C ((uint16_t)0x0000)
44 #define I2C_MODE_SMBUSDEVICE ((uint16_t)0x0002)
45 #define I2C_MODE_SMBUSHOST ((uint16_t)0x000A)
47 /* I2C_duty_cycle_in_fast_mode */
48 #define I2C_DUTYCYCLE_16_9 ((uint16_t)0x4000)
49 #define I2C_DUTYCYCLE_2 ((uint16_t)0xBFFF)
51 /* I2C_cknowledgementy */
52 #define I2C_ACK_ENABLE ((uint16_t)0x0400)
53 #define I2C_ACK_DISABLE ((uint16_t)0x0000)
55 /* I2C_transfer_direction */
56 #define I2C_DIRECTION_TRANSMITTER ((uint8_t)0x00)
57 #define I2C_DIRECTION_RECEIVER ((uint8_t)0x01)
59 /* I2C_acknowledged_address_defines */
60 #define I2C_ACKNOWLEDGEDADDRESS_7BIT ((uint16_t)0x4000)
61 #define I2C_ACKNOWLEDGEDADDRESS_10BIT ((uint16_t)0xC000)
64 #define I2C_REGISTER_CR1 ((uint8_t)0x00)
65 #define I2C_REGISTER_CR2 ((uint8_t)0x04)
66 #define I2C_REGISTER_OAR1 ((uint8_t)0x08)
67 #define I2C_REGISTER_OAR2 ((uint8_t)0x0C)
68 #define I2C_REGISTER_DR ((uint8_t)0x10)
69 #define I2C_REGISTER_SR1 ((uint8_t)0x14)
70 #define I2C_REGISTER_SR2 ((uint8_t)0x18)
71 #define I2C_REGISTER_CCR ((uint8_t)0x1C)
72 #define I2C_REGISTER_TRISE ((uint8_t)0x20)
74 /* I2C_SMBus_alert_pin_level */
75 #define I2C_SMBUSALERT_LOW ((uint16_t)0x2000)
76 #define I2C_SMBUSALERT_HIGH ((uint16_t)0xDFFF)
78 /* I2C_PEC_position */
79 #define I2C_PECPOSITION_NEXT ((uint16_t)0x0800)
80 #define I2C_PECPOSITION_CURRENT ((uint16_t)0xF7FF)
82 /* I2C_interrupts_definition */
83 #define I2C_IT_BUF ((uint16_t)0x0400)
84 #define I2C_IT_EVT ((uint16_t)0x0200)
85 #define I2C_IT_ERR ((uint16_t)0x0100)
87 /* I2C_interrupts_definition */
88 #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
89 #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
90 #define I2C_IT_PECERR ((uint32_t)0x01001000)
91 #define I2C_IT_OVR ((uint32_t)0x01000800)
92 #define I2C_IT_AF ((uint32_t)0x01000400)
93 #define I2C_IT_ARLO ((uint32_t)0x01000200)
94 #define I2C_IT_BERR ((uint32_t)0x01000100)
95 #define I2C_IT_TXE ((uint32_t)0x06000080)
96 #define I2C_IT_RXNE ((uint32_t)0x06000040)
97 #define I2C_IT_STOPF ((uint32_t)0x02000010)
98 #define I2C_IT_ADD10 ((uint32_t)0x02000008)
99 #define I2C_IT_BTF ((uint32_t)0x02000004)
100 #define I2C_IT_ADDR ((uint32_t)0x02000002)
101 #define I2C_IT_SB ((uint32_t)0x02000001)
103 /* SR2 register flags */
104 #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
105 #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
106 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
107 #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
108 #define I2C_FLAG_TRA ((uint32_t)0x00040000)
109 #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
110 #define I2C_FLAG_MSL ((uint32_t)0x00010000)
112 /* SR1 register flags */
113 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
114 #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
115 #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
116 #define I2C_FLAG_OVR ((uint32_t)0x10000800)
117 #define I2C_FLAG_AF ((uint32_t)0x10000400)
118 #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
119 #define I2C_FLAG_BERR ((uint32_t)0x10000100)
120 #define I2C_FLAG_TXE ((uint32_t)0x10000080)
121 #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
122 #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
123 #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
124 #define I2C_FLAG_BTF ((uint32_t)0x10000004)
125 #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
126 #define I2C_FLAG_SB ((uint32_t)0x10000001)
129 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
130 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
131 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
132 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
133 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
136 #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
139 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
142 #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
145 #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
149 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
150 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
153 #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
156 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
159 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
162 #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
165 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
170 #define CR1_PE_SET ((uint16_t)0x0001)
171 #define CR1_PE_RESET ((uint16_t)0xFFFE)
174 #define CR1_START_SET ((uint16_t)0x0100)
175 #define CR1_START_RESET ((uint16_t)0xFEFF)
178 #define CR1_STOP_SET ((uint16_t)0x0200)
179 #define CR1_STOP_RESET ((uint16_t)0xFDFF)
182 #define CR1_ACK_SET ((uint16_t)0x0400)
183 #define CR1_ACK_RESET ((uint16_t)0xFBFF)
186 #define CR1_ENGC_SET ((uint16_t)0x0040)
187 #define CR1_ENGC_RESET ((uint16_t)0xFFBF)
190 #define CR1_SWRST_SET ((uint16_t)0x8000)
191 #define CR1_SWRST_RESET ((uint16_t)0x7FFF)
194 #define CR1_PEC_SET ((uint16_t)0x1000)
195 #define CR1_PEC_RESET ((uint16_t)0xEFFF)
198 #define CR1_ENPEC_SET ((uint16_t)0x0020)
199 #define CR1_ENPEC_RESET ((uint16_t)0xFFDF)
202 #define CR1_ENARP_SET ((uint16_t)0x0010)
203 #define CR1_ENARP_RESET ((uint16_t)0xFFEF)
205 /* I2C NOSTRETCH mask */
206 #define CR1_NOSTRETCH_SET ((uint16_t)0x0080)
207 #define CR1_NOSTRETCH_RESET ((uint16_t)0xFF7F)
209 /* I2C registers Masks */
210 #define CR1_CLEAR_MASK ((uint16_t)0xFBF5)
213 #define CR2_DMAEN_SET ((uint16_t)0x0800)
214 #define CR2_DMAEN_RESET ((uint16_t)0xF7FF)
217 #define CR2_LAST_SET ((uint16_t)0x1000)
218 #define CR2_LAST_RESET ((uint16_t)0xEFFF)
221 #define CR2_FREQ_RESET ((uint16_t)0xFFC0)
223 #define CR2_FREQ_36MHZ ((uint16_t)0x100100)
226 #define OAR1_ADD0_SET ((uint16_t)0x0001)
227 #define OAR1_ADD0_RESET ((uint16_t)0xFFFE)
229 /* I2C ENDUAL mask */
230 #define OAR2_ENDUAL_SET ((uint16_t)0x0001)
231 #define OAR2_ENDUAL_RESET ((uint16_t)0xFFFE)
234 #define OAR2_ADD2_RESET ((uint16_t)0xFF01)
237 #define CCR_FS_SET ((uint16_t)0x8000)
240 #define CCR_CCR_SET ((uint16_t)0x0FFF)
271 #endif /* STM32_I2C_H */