4 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
5 * Copyright 2000 Bernardo Innocenti <bernie@develer.com>
6 * This file is part of DevLib - See devlib/README for information.
11 * \author Bernardo Innocenti <bernie@develer.com>
13 * \brief Low-level timer module for AVR
18 *#* Revision 1.19 2004/10/19 08:56:41 bernie
19 *#* TIMER_STROBE_ON, TIMER_STROBE_OFF, TIMER_STROBE_INIT: Move from timer_avr.h to timer.h, where they really belong.
21 *#* Revision 1.18 2004/09/20 03:31:03 bernie
22 *#* Fix racy racy code.
24 *#* Revision 1.17 2004/09/14 21:07:09 bernie
25 *#* Include hw.h explicitly.
27 *#* Revision 1.16 2004/09/06 21:49:26 bernie
28 *#* CONFIG_TIMER_STROBE: be tolerant with missing optional macro.
30 *#* Revision 1.15 2004/08/25 14:12:08 rasky
31 *#* Aggiornato il comment block dei log RCS
33 *#* Revision 1.14 2004/08/24 16:27:01 bernie
34 *#* Add missing headers.
36 *#* Revision 1.13 2004/08/24 14:30:11 bernie
37 *#* Use new-style config macros for drv/timer.c
39 *#* Revision 1.12 2004/08/10 06:59:45 bernie
40 *#* CONFIG_TIMER_STROBE: Define no-op default macros.
42 *#* Revision 1.11 2004/08/03 15:53:17 aleph
45 *#* Revision 1.10 2004/08/02 20:20:29 aleph
46 *#* Merge from project_ks
48 *#* Revision 1.9 2004/07/22 02:01:14 bernie
49 *#* Use TIMER_PRESCALER consistently.
51 #ifndef DRV_TIMER_AVR_H
52 #define DRV_TIMER_AVR_H
54 #include <arch_config.h> // ARCH_BOARD_KC
58 #include <avr/signal.h>
60 #if defined(ARCH_BOARD_KC) && (ARCH & ARCH_BOARD_KC)
66 * Values for CONFIG_TIMER.
68 * Select which hardware timer interrupt to use for system clock and softtimers.
69 * \note The timer 1 overflow mode set the timer as a 24 kHz PWM.
71 #define TIMER_ON_OUTPUT_COMPARE0 1
72 #define TIMER_ON_OVERFLOW1 2
73 #define TIMER_ON_OUTPUT_COMPARE2 3
76 /* Not needed, IRQ timer flag cleared automatically */
77 #define timer_hw_irq() do {} while (0)
79 #define TIMER_PRESCALER 64
82 * System timer: additional division after the prescaler
83 * 12288000 / 64 / 192 (0..191) = 1 ms
85 #define OCR_DIVISOR (CLOCK_FREQ / TIMER_PRESCALER / TICKS_PER_SEC - 1) /* 191 */
87 /*! HW dependent timer initialization */
88 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
90 //! Type of time expressed in ticks of the hardware high-precision timer
91 typedef uint8_t hptime_t;
93 static void timer_hw_init(void)
96 DISABLE_IRQSAVE(flags);
98 /* Reset Timer flags */
99 TIFR = BV(OCF0) | BV(TOV0);
101 /* Setup Timer/Counter interrupt */
102 ASSR = 0x00; /* Internal system clock */
103 TCCR0 = BV(WGM01) /* Clear on Compare match */
104 #if TIMER_PRESCALER == 64
107 #error Unsupported value of TIMER_PRESCALER
110 TCNT0 = 0x00; /* Initialization of Timer/Counter */
111 OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
113 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
117 ENABLE_IRQRESTORE(flags);
120 //! Frequency of the hardware high precision timer
121 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
123 INLINE hptime_t timer_hw_hpread(void)
128 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
130 //! Type of time expressed in ticks of the hardware high precision timer
131 typedef uint16_t hptime_t;
133 static void timer_hw_init(void)
136 DISABLE_IRQSAVE(flags);
138 /* Reset Timer overflow flag */
141 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. When changing freq or
142 resolution (top of TCNT), change TIMER_HW_HPTICKS_PER_SEC too */
144 TCCR1A &= ~BV(WGM10);
145 TCCR1B |= BV(WGM12) | BV(CS10);
146 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
148 TCNT1 = 0x00; /* initialization of Timer/Counter */
150 /* Enable timer interrupt: Timer/Counter1 Overflow */
153 ENABLE_IRQRESTORE(flags);
156 //! Frequency of the hardware high precision timer
157 #define TIMER_HW_HPTICKS_PER_SEC (24000ul * 512)
159 INLINE hptime_t timer_hw_hpread(void)
164 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
166 //! Type of time expressed in ticks of the hardware high precision timer
167 typedef uint8_t hptime_t;
169 static void timer_hw_init(void)
172 DISABLE_IRQSAVE(flags);
174 /* Reset Timer flags */
175 TIFR = BV(OCF2) | BV(TOV2);
177 /* Setup Timer/Counter interrupt */
179 #if TIMER_PRESCALER == 64
180 | BV(CS21) | BV(CS20)
182 #error Unsupported value of TIMER_PRESCALER
185 /* Clear on Compare match & prescaler = 64, internal sys clock.
186 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
187 TCNT2 = 0x00; /* initialization of Timer/Counter */
188 OCR2 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
190 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
194 ENABLE_IRQRESTORE(flags);
197 //! Frequency of the hardware high precision timer
198 #define TIMER_HW_HPTICKS_PER_SEC (CLOCK_FREQ / TIMER_PRESCALER)
200 INLINE hptime_t timer_hw_hpread(void)
206 #error Unimplemented value for CONFIG_TIMER
207 #endif /* CONFIG_TIMER */
210 #if (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
212 #define DEFINE_TIMER_ISR \
213 static void timer_handler(void)
218 * Timer 1 overflow irq handler. It's called at the frequency of the timer 1
219 * PWM (should be 24 kHz). It's too much for timer purposes, so the interrupt
220 * handler is really a counter that call the true handler in timer.c
223 SIGNAL(SIG_OVERFLOW1)
225 #if (ARCH & ARCH_BOARD_KC)
227 * Super-optimization-hack: switch CPU ADC mux here, ASAP after the start
228 * of conversion (auto-triggered with timer 1 overflow).
229 * The switch can be done 2 ADC cycles after start of conversion.
230 * The handler prologue takes a little more than 32 CPU cycles: with
231 * the prescaler at 1/16 the timing should be correct even at the start
234 * The switch is synchronized with the ADC handler using _adc_trigger_lock.
236 * Mel (A Real Programmer)
238 extern uint8_t _adc_idx_next;
239 extern bool _adc_trigger_lock;
241 if (!_adc_trigger_lock)
244 * Disable free-running mode to avoid starting a
245 * new conversion before the ADC handler has read
246 * the ongoing one. This condition could occur
247 * under very high interrupt load and would have the
248 * unwanted effect of reading from the wrong ADC
251 * NOTE: writing 0 to ADSC and ADIF has no effect.
253 ADCSRA = ADCSRA & ~(BV(ADFR) | BV(ADIF) | BV(ADSC));
255 ADC_SETCHN(_adc_idx_next);
256 _adc_trigger_lock = true;
258 #endif // ARCH_BOARD_KC
261 * How many timer overflows we must count before calling the real
263 * When the timer is programmed to overflow at 24 kHz, a value of
264 * 24 will result in 1ms between each call.
266 #define TIMER1_OVF_COUNT 24
267 //#warning TIMER1_OVF_COUNT for timer at 12 kHz
268 //#define TIMER1_OVF_COUNT 12
270 static uint8_t count = TIMER1_OVF_COUNT;
276 count = TIMER1_OVF_COUNT;
280 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
282 #define DEFINE_TIMER_ISR \
283 SIGNAL(SIG_OUTPUT_COMPARE0)
285 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
287 #define DEFINE_TIMER_ISR \
288 SIGNAL(SIG_OUTPUT_COMPARE2)
291 #error Unimplemented value for CONFIG_TIMER
292 #endif /* CONFIG_TIMER */
294 #endif /* DRV_TIMER_AVR_H */