#if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
- /**
- * With a 18.420MHz cristal, master clock is:
- * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
- */
+ /*
+ * With a 18.420MHz cristal, master clock is:
+ * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
+ */
#define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
#define PLL_DIV_VAL 14
#define AT91MCK_PRES PMC_PRES_CLK_2
- /**
- * Register I/O adresses.
- * \{
- */
+ /*
+ * Register I/O adresses.
+ */
#define MC_BASE 0xFFFFFF00
#define MC_FMR_OFF 0x00000060
#define MC_FWS_2R3W 0x00000100
#elif CPU_ARM_SAM7X
#define PMC_PIO_CLK_EN ((1 << 2) | (1 << 3))
#else
- #error CPU non supported
+ #error CPU not supported
#endif
#define CKGR_MOR_OFF 0x00000020
#define RSTC_KEY 0xA5000000
#define RSTC_URSTEN (1 << 0)
+ #define ARM_MODE_USR 0x10
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_ABORT 0x17
#define ARM_MODE_UNDEF 0x1B
+ #define ARM_MODE_SYS 0x1F
#else
#error No register I/O definition for selected ARM CPU
/*
* Initialize user stack pointer.
*/
- ldr r13, =__stack_end
+ /* msr CPSR_c, #ARM_MODE_SYS | 0xC0 */
+ ldr r13, =__stack_end
/*