*
* -->
*
- * \brief ATSAM3 clock setup.
+ * \brief Atmel SAM3 clock setup.
*
* \author Stefano Fedrigo <aleph@develer.com>
*/
#include "clock_sam3.h"
-#include <io/sam3_pmc.h>
-#include <io/sam3_sysctl.h>
-#include <io/sam3_flash.h>
#include <cfg/compiler.h>
#include <cfg/macros.h>
+#include <io/sam3.h>
/* Frequency of board main oscillator */
+// TODO: wizard config
#define BOARDOSC_FREQ 12000000
/* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
}
}
- // Bit 29 must always be set to 1
- return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
+ return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul);
}
{
uint32_t timeout;
- /* Set 4 wait states for flash access, needed for higher CPU clock rates */
- EEFC_FMR = EEFC_FMR_FWS(3);
+ /* Disable watchdog */
+ WDT_MR = BV(WDT_WDDIS);
+#if CPU_CM3_SAM3X
+ /* Set wait states for flash access, needed for higher CPU clock rates */
+ EEFC0_FMR = EEFC_FMR_FWS(2);
+ EEFC1_FMR = EEFC_FMR_FWS(2);
+#else
+ EEFC0_FMR = EEFC_FMR_FWS(3);
+
+ // TODO: check if this is needed in sam3n-ek too, very slow start-up
// Select external slow clock
- if (!(SUPC_SR_R & SUPC_SR_OSCSEL))
+ if (!(SUPC_SR & BV(SUPC_SR_OSCSEL)))
{
- SUPC_CR_R = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
- while (!(SUPC_SR_R & SUPC_SR_OSCSEL));
+ SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5);
+ while (!(SUPC_SR & BV(SUPC_SR_OSCSEL)));
}
+#endif
// Initialize main oscillator
- if (!(CKGR_MOR_R & CKGR_MOR_MOSCSEL))
+ if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
{
- CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+ CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR_R & PMC_SR_MOSCXTS) && --timeout);
+ while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
}
// Switch to external oscillator
- CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+ CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR_R & PMC_SR_MOSCSELS) && --timeout);
+ while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout);
- PMC_MCKR_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M) | PMC_MCKR_CSS_MAIN_CLK;
+ PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+ while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
// Initialize and enable PLL clock
- CKGR_PLLR_R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
+ CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1);
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR_R & PMC_SR_LOCK) && --timeout);
+ while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
- PMC_MCKR_R = PMC_MCKR_CSS_MAIN_CLK;
+ PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+ while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
- PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
+ PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+ while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
+
+ /* Enable clock on PIO for inputs */
+ // TODO: move this in gpio_init() for better power management?
+#if CPU_CM3_SAM3X
+ PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID)
+ | BV(PIOD_ID) | BV(PIOE_ID) | BV(PIOF_ID);
+#else
+ PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID);
+#endif
}