* \author Andrea Righi <arighi@develer.com>
*/
+#include "clock_stm32.h"
+
#include <cfg/compiler.h>
#include <cfg/debug.h>
+
#include <io/stm32.h>
-#include "clock_stm32.h"
struct RCC *RCC;
INLINE uint16_t pll_clock(void)
{
- int div, mul;
+ unsigned int div, mul;
/* Hopefully this is evaluate at compile time... */
for (div = 2; div; div--)
for (mul = 2; mul <= 16; mul++)
- if (CPU_FREQ >= (PLL_VCO / div * mul))
+ if (CPU_FREQ <= (PLL_VCO / div * mul))
break;
return mul << 8 | div;
}
rcc_pll_config();
while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
+ /* Configure USB clock (48MHz) */
+ *CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
+ /* Configure ADC clock: PCLK2 (9MHz) */
+ RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
+ RCC->CFGR |= RCC_PCLK2_DIV8;
+ /* Configure system clock dividers: PCLK2 (72MHz) */
+ RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
+ RCC->CFGR |= RCC_HCLK_DIV1 << 3;
+ /* Configure system clock dividers: PCLK1 (36MHz) */
+ RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
+ RCC->CFGR |= RCC_HCLK_DIV2;
+ /* Configure system clock dividers: HCLK */
+ RCC->CFGR &= CFGR_HPRE_RESET_MASK;
+ RCC->CFGR |= RCC_SYSCLK_DIV1;
+
/* Set 1 wait state for the flash memory */
- *(reg32_t *)0x40022000 = 0x12;
+ *(reg32_t *)FLASH_BASE = 0x12;
/* Clock the system from the PLL */
rcc_set_clock_source(RCC_SYSCLK_PLLCLK);