start_r(i2c, slave_addr);
}
-static void i2c_stm32_put(I2c *i2c, const uint8_t data)
+static void i2c_stm32_putc(I2c *i2c, const uint8_t data)
{
i2c->hw->base->DR = data;
}
}
-static uint8_t i2c_stm32_get(I2c *i2c)
+static uint8_t i2c_stm32_getc(I2c *i2c)
{
if (i2c->hw->cached)
{
static const I2cVT i2c_stm32_vt =
{
.start = i2c_stm32_start,
- .get = i2c_stm32_get,
- .put = i2c_stm32_put,
- .send = i2c_swSend,
- .recv = i2c_swRecv,
+ .getc = i2c_stm32_getc,
+ .putc = i2c_stm32_putc,
+ .write = i2c_genericWrite,
+ .read = i2c_genericRead,
};
-struct I2cHardware i2c_stm32_hw[] =
+static struct I2cHardware i2c_stm32_hw[] =
{
{ /* I2C1 */
.base = (struct stm32_i2c *)I2C1_BASE,
},
};
-MOD_DEFINE(i2c);
-
/**
* Initialize I2C module.
*/
i2c->hw->base->TRISE |= (CR2_FREQ_36MHZ + 1);
i2c->hw->base->CR1 |= CR1_PE_SET;
-
- MOD_INIT(i2c);
}