/* End USART0 macros */
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
#ifndef SER_UART1_BUS_TXINIT
/**
#define SER_UART1_BUS_TXINIT do { \
PIOA_PDR = BV(RXD1) | BV(TXD1); \
} while (0)
- #elif CPU_CM3_AT91SAM3
+ #elif CPU_CM3_SAM3
#define SER_UART1_BUS_TXINIT do { \
PIOB_PDR = BV(RXD1) | BV(TXD1); \
} while (0)
* Default TXINIT macro - invoked in spi_init()
* The default is no action.
*/
- #if CPU_CM3_AT91SAM3
+ #if CPU_CM3_SAM3
#define SER_SPI0_BUS_TXINIT do { \
/* Disable PIO on SPI pins */ \
- PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO) | BV(30); \
+ PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO); \
/* PIO is peripheral A */ \
PIOA_ABCDSR1 &= ~(BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO)); \
PIOA_ABCDSR2 &= ~(BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO)); \
- /* Peripheral B for chip select for display (FIXME: move away from driver) */ \
- PIOA_ABCDSR1 |= BV(30); \
- PIOA_ABCDSR2 &= ~BV(30); \
} while (0)
#else
#define SER_SPI0_BUS_TXINIT do { \
AIC_EOICR = 0; \
} while (0)
-#elif CPU_CM3_AT91SAM3
+#elif CPU_CM3_SAM3
/** Inform hw that we have served the IRQ */
#define SER_INT_ACK do { /* nop */ } while (0)
/* TX and RX buffers */
static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
#endif
};
static ISR_PROTO(uart0_irq_dispatcher);
-#if !CPU_CM3_AT91SAM3U
+#if !CPU_CM3_SAM3U
static ISR_PROTO(uart1_irq_dispatcher);
#endif
static ISR_PROTO(spi0_irq_handler);
* Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
* SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
*/
- SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS); // | SPI_PCS_2;
+ SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
/*
* Set SPI mode.
* At reset clock division factor is set to 0, that is
* *forbidden*. Set SPI clock to minimum to keep it valid.
+ * Set all possible chip select registers in case user manually
+ * change CPS field in SPI_MR.
*/
SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+ SPI0_CSR1 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+ SPI0_CSR2 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+ SPI0_CSR3 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
/* Disable all irqs */
SPI0_IDR = 0xFFFFFFFF;
* Set SPI mode.
* At reset clock division factor is set to 0, that is
* *forbidden*. Set SPI clock to minimum to keep it valid.
+ * Set all possible chip select registers in case user manually
+ * change chip select.
*/
SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+ SPI1_CSR1 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+ SPI1_CSR2 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
+ SPI1_CSR3 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
/* Disable all SPI irqs */
SPI1_IDR = 0xFFFFFFFF;