#include <cfg/compiler.h>
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256
#define FLASH_BASE 0x100000UL
#define RAM_BASE 0x200000UL
#define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
#define MC_BASE 0xFFFFFF00 ///< Memory controller base.
- #if CPU_ARM_AT91SAM7X256
+ #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
#define CAN_BASE 0xFFFD0000 ///< PWM controller base address.
#define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address.
#define SPI0_BASE 0xFFFE0000 ///< SPI0 base address.
#include "at91_pio.h"
#include "at91_us.h"
#include "at91_dbgu.h"
+#include "at91_tc.h"
+#include "at91_adc.h"
+#include "at91_pwm.h"
+#include "at91_spi.h"
+#include "at91_twi.h"
//TODO: add other peripherals
/**
* Peripheral Identifiers and Interrupts
*\{
*/
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128
#define FIQ_ID 0 ///< Fast interrupt ID.
#define SYSC_ID 1 ///< System controller interrupt.
#define US0_ID 6 ///< USART 0 ID.
#define IRQ0_ID 30 ///< External interrupt 0 ID.
#define IRQ1_ID 31 ///< External interrupt 1 ID.
- #if CPU_ARM_AT91SAM7X256
+ #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
#define PIOA_ID 2 ///< Parallel A I/O controller ID.
#define PIOB_ID 3 ///< Parallel B I/O controller ID.
#define SPI0_ID 4 ///< Serial peripheral interface 0 ID.
/* ID 3 is reserved */
#define ADC_ID 4 ///< Analog to digital converter ID.
#define SPI_ID 5 ///< Serial peripheral interface ID.
-
+ #define SPI0_ID SPI_ID ///< Alias
#endif
#else
/*\}*/
/**
- * USART pins name
+ * USART & DEBUG pin names
*\{
*/
#if CPU_ARM_AT91SAM7S256
#define TXD0 6
#define RXD1 21
#define TXD1 22
-
-#elif CPU_ARM_AT91SAM7X256
- #define RXD0 0 // PA0
- #define TXD0 1 // PA1
- #define RXD1 5 // PA5
- #define TXD1 6 // PA6
-
+ #define DTXD 10
+ #define DRXD 9
+#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+ #define RXD0 0 // PA0
+ #define TXD0 1 // PA1
+ #define RXD1 5 // PA5
+ #define TXD1 6 // PA6
+ #define DTXD 28 // PA28
+ #define DRXD 27 // PA27
#else
- #error No USART pins name definition for selected ARM CPU
-
+ #error No USART & debug pin names definition for selected ARM CPU
#endif
/*\}*/
*\{
*/
#if CPU_ARM_AT91SAM7S256
- #define NPCS0 11 // Same as NSS pin.
- #define MISO 12
- #define MOSI 13
- #define SPCK 14
+ #define SPI0_NPCS0 11 // Same as NSS pin.
+ #define SPI0_MISO 12
+ #define SPI0_MOSI 13
+ #define SPI0_SPCK 14
-#elif CPU_ARM_AT91SAM7X256
+#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
#define SPI0_NPCS0 12 // Same as NSS pin. PA12
#define SPI0_NPCS1 13 // PA13
#define SPI0_NPCS2 14 // PA14
#endif
/*\}*/
+/**
+ * Timer counter pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+ #define TIOA0 23 // PB23
+ #define TIOB0 24 // PB24
+ #define TIOA1 25 // PB25
+ #define TIOB1 26 // PB26
+ #define TIOA2 27 // PB27
+ #define TIOB2 28 // PB28
+
+#elif CPU_ARM_AT91SAM7S256
+ #define TIOA0 0 // PA0
+ #define TIOB0 1 // PA1
+ #define TIOA1 15 // PA15
+ #define TIOB1 16 // PA16
+ #define TIOA2 26 // PA26
+ #define TIOB2 27 // PA27
+
+#else
+ #error No Timer Conter pins name definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+/**
+ * PWM pins definition.
+ *\{
+ */
+#define PWM_PIO_FUNCTION_A 1
+
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+ #if PWM_PIO_FUNCTION_A
+ #define PWM0 19 // PB19
+ #define PWM1 20 // PB20
+ #define PWM2 21 // PB21
+ #define PWM3 22 // PB22
+ #else
+ #define PWM0 27 // PB27
+ #define PWM1 28 // PB28
+ #define PWM2 29 // PB29
+ #define PWM3 30 // PB30
+ #endif
+
+
+#elif CPU_ARM_AT91SAM7S256
+ #define PWM0 11 // PA11
+ #define PWM1 12 // PA12
+ #define PWM2 13 // PA13
+ #define PWM3 14 // PA14
+
+#else
+ #error No PWM pins name definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+/**
+ * TWI pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+ #define TWD 10
+ #define TWCK 11
+#else
+ #error No TWI pin names definition for selected ARM CPU
+#endif
+
+/**
+ * ADC pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256
+ #define ADTRG 18 // PB18
+ #define AD0 23 // PB27
+ #define AD1 24 // PB28
+ #define AD2 25 // PB29
+ #define AD3 26 // PB30
+
+#elif CPU_ARM_AT91SAM7S256
+ #define ADTRG 18 // PA8
+ #define AD0 0 // PA17
+ #define AD1 1 // PA18
+ #define AD2 15 // PA19
+ #define AD3 16 // PA20
+
+#else
+ #error No Timer Conter pin names definition for selected ARM CPU
+
+#endif
+/*\}*/
+
#endif /* AT91SAM7_H */