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Minor fixes in AT91 ADC module.
[bertos.git]
/
bertos
/
cfg
/
cfg_adc.h
diff --git
a/bertos/cfg/cfg_adc.h
b/bertos/cfg/cfg_adc.h
index 25eea527ea46997fc20e80d82e05919bd0d28147..35e5866188083612981dd9564c00c186b7d833e7 100644
(file)
--- a/
bertos/cfg/cfg_adc.h
+++ b/
bertos/cfg/cfg_adc.h
@@
-30,7
+30,7
@@
*
* -->
*
*
* -->
*
- * \brief Configuration file for ADC module.
+ * \brief Configuration file for
the
ADC module.
*
* \version $Id$
* \author Daniele Basile <asterix@develer.com>
*
* \version $Id$
* \author Daniele Basile <asterix@develer.com>
@@
-42,55
+42,71
@@
/**
* Module logging level.
*
/**
* Module logging level.
*
- * $WIZARD = { "type" : "enum", "value_list" : "log_level" }
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_level"
*/
#define ADC_LOG_LEVEL LOG_LVL_INFO
/**
* Module logging format.
*
*/
#define ADC_LOG_LEVEL LOG_LVL_INFO
/**
* Module logging format.
*
- * $WIZARD = { "type" : "enum", "value_list" : "log_format" }
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_format"
*/
#define ADC_LOG_FORMAT LOG_FMT_VERBOSE
/**
*/
#define ADC_LOG_FORMAT LOG_FMT_VERBOSE
/**
- * Frequency clock for ADC conversion.
+ * Clock Frequency for ADC conversion.
+ * This frequency will be rounded down to an integer
+ * submultiple of CPU_FREQ.
*
*
- * $WIZARD = { "type" : "int" }
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "at91"
+ * $WIZ$ max = 5000000
*/
#define CONFIG_ADC_CLOCK 4800000UL
/**
*/
#define CONFIG_ADC_CLOCK 4800000UL
/**
- * Minimum time for start
up a conversion in micro second
.
+ * Minimum time for start
ing up a conversion [us]
.
*
*
- * $WIZARD = { "type" : "int" }
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 20
+ * $WIZ$ supports = "at91"
*/
#define CONFIG_ADC_STARTUP_TIME 20
/**
*/
#define CONFIG_ADC_STARTUP_TIME 20
/**
- * Minimum time for sample and hold
in nano second
.
+ * Minimum time for sample and hold
[ns]
.
*
*
- * $WIZARD = { "type" : "int" }
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 600
+ * $WIZ$ supports = "at91"
*/
#define CONFIG_ADC_SHTIME 834
/**
*/
#define CONFIG_ADC_SHTIME 834
/**
- * ADC
setting for AVR target
.
+ * ADC
Voltage Reference
.
*
*
- * $WIZARD = {"type" : "int" }
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "avr_adc_refs"
+ * $WIZ$ supports = "avr"
*/
*/
-#define CONFIG_ADC_AVR_REF 1
-/*
- * ADC setting for AVR target.
+#define CONFIG_ADC_AVR_REF ADC_AVR_AVCC
+
+/**
+ * ADC clock divisor from main crystal.
*
*
- * $WIZARD = {"type" : "int" }
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ max = 128
+ * $WIZ$ supports = "avr"
*/
#define CONFIG_ADC_AVR_DIVISOR 2
/**
*/
#define CONFIG_ADC_AVR_DIVISOR 2
/**
- * Enable AD
S strobe
.
+ * Enable AD
C strobe for debugging ADC ISR
.
*
*
- * $WIZ
ARD = {"type" : "boolean" }
+ * $WIZ
$ type = "boolean"
*/
#define CONFIG_ADC_STROBE 0
*/
#define CONFIG_ADC_STROBE 0