*/
#define CONFIG_SPI_CLOCK_POL SPI_NORMAL_LOW
/**
* SPI clock phase you can choose sample on first edge or
* sample on second clock edge (AVR only)
*/
#define CONFIG_SPI_CLOCK_POL SPI_NORMAL_LOW
/**
* SPI clock phase you can choose sample on first edge or
* sample on second clock edge (AVR only)