-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
-#define CONFIG_SPI_CLOCK_POL 0
-
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
-#define CONFIG_SPI_CLOCK_PHASE 0
+/**
+ * SPI clock phase you can choose sample on first edge or
+ * sample on second clock edge (AVR only)
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_phase"
+ */
+#define CONFIG_SPI_CLOCK_PHASE SPI_SAMPLE_ON_FIRST_EDGE