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Add the isComplete overload per the cpu selection page
[bertos.git]
/
bertos
/
cpu
/
arm
/
drv
/
pwm_at91.c
diff --git
a/bertos/cpu/arm/drv/pwm_at91.c
b/bertos/cpu/arm/drv/pwm_at91.c
index 142b9feb80668a37f4e08c34fbb5baac0974cc9a..e0706812d83718142d56f82b54f52bf23b8f259e 100644
(file)
--- a/
bertos/cpu/arm/drv/pwm_at91.c
+++ b/
bertos/cpu/arm/drv/pwm_at91.c
@@
-34,12
+34,18
@@
* \brief PWM hardware-specific implementation
*
* \version $Id$
* \brief PWM hardware-specific implementation
*
* \version $Id$
- *
* \author Daniele Basile <asterix@develer.com>
*/
#include "pwm_at91.h"
* \author Daniele Basile <asterix@develer.com>
*/
#include "pwm_at91.h"
-#include "hw_cpu.h"
+#include "hw/pwm_map.h"
+#include "hw/hw_cpu.h"
+#include "cfg/cfg_pwm.h"
+
+// Define logging setting (for cfg/log.h module).
+#define LOG_LEVEL PWM_LOG_LEVEL
+#define LOG_FORMAT PWM_LOG_FORMAT
+#include <cfg/log.h>
#include <cfg/macros.h>
#include <cfg/debug.h>
#include <cfg/macros.h>
#include <cfg/debug.h>
@@
-56,6
+62,7
@@
static PwmChannel pwm_map[PWM_CNT] =
{
{//PWM Channel 0
.duty_zero = false,
{
{//PWM Channel 0
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM0),
.mode_reg = &PWM_CMR0,
.duty_reg = &PWM_CDTY0,
.pwm_pin = BV(PWM0),
.mode_reg = &PWM_CMR0,
.duty_reg = &PWM_CDTY0,
@@
-64,6
+71,7
@@
static PwmChannel pwm_map[PWM_CNT] =
},
{//PWM Channel 1
.duty_zero = false,
},
{//PWM Channel 1
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM1),
.mode_reg = &PWM_CMR1,
.duty_reg = &PWM_CDTY1,
.pwm_pin = BV(PWM1),
.mode_reg = &PWM_CMR1,
.duty_reg = &PWM_CDTY1,
@@
-72,6
+80,7
@@
static PwmChannel pwm_map[PWM_CNT] =
},
{//PWM Channel 2
.duty_zero = false,
},
{//PWM Channel 2
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM2),
.mode_reg = &PWM_CMR2,
.duty_reg = &PWM_CDTY2,
.pwm_pin = BV(PWM2),
.mode_reg = &PWM_CMR2,
.duty_reg = &PWM_CDTY2,
@@
-80,6
+89,7
@@
static PwmChannel pwm_map[PWM_CNT] =
},
{//PWM Channel 3
.duty_zero = false,
},
{//PWM Channel 3
.duty_zero = false,
+ .pol = false,
.pwm_pin = BV(PWM3),
.mode_reg = &PWM_CMR3,
.duty_reg = &PWM_CDTY3,
.pwm_pin = BV(PWM3),
.mode_reg = &PWM_CMR3,
.duty_reg = &PWM_CDTY3,
@@
-111,7
+121,7
@@
void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
{
period = CLOCK_FREQ / (BV(i) * freq);
for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
{
period = CLOCK_FREQ / (BV(i) * freq);
-//
TRACEMSG("period[%d], prescale[%d]
", period, i);
+//
LOG_INFO("period[%ld], prescale[%d]\n
", period, i);
if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
{
//Clean previous channel prescaler, and set new
if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
{
//Clean previous channel prescaler, and set new
@@
-123,9
+133,7
@@
void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
}
}
}
}
- PWM_ENA = BV(dev);
-
-// TRACEMSG("PWM ch[%d] period[%d]", dev, period);
+ LOG_INFO("PWM ch[%d] period[%ld]\n", dev, period);
}
/**
}
/**
@@
-150,12
+158,24
@@
void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
else
{
ASSERT(PWM_CCNT0);
else
{
ASSERT(PWM_CCNT0);
+ /*
+ * If polarity flag is true we must invert
+ * PWM polarity.
+ */
+ if (pwm_map[dev].pol)
+ {
+ duty = (uint16_t)*pwm_map[dev].period_reg - duty;
+ LOG_INFO("Inverted duty[%d], pol[%d]\n", duty, pwm_map[dev].pol);
+ }
+
PWM_PIO_PDR = pwm_map[dev].pwm_pin;
*pwm_map[dev].update_reg = duty;
pwm_map[dev].duty_zero = false;
}
PWM_PIO_PDR = pwm_map[dev].pwm_pin;
*pwm_map[dev].update_reg = duty;
pwm_map[dev].duty_zero = false;
}
-// TRACEMSG("PWM ch[%d] duty[%d], period[%ld]", dev, duty, *pwm_map[dev].period_reg);
+ PWM_ENA = BV(dev);
+
+ LOG_INFO("PWM ch[%d] duty[%d], period[%ld]\n", dev, duty, *pwm_map[dev].period_reg);
}
}
@@
-176,6
+196,14
@@
void pwm_hw_disable(PwmDev dev)
PWM_PIO_PER = pwm_map[dev].pwm_pin;
}
PWM_PIO_PER = pwm_map[dev].pwm_pin;
}
+/**
+ * Set PWM polarity to select pwm channel
+ */
+void pwm_hw_setPolarity(PwmDev dev, bool pol)
+{
+ pwm_map[dev].pol = pol;
+ LOG_INFO("Set pol[%d]\n", pwm_map[dev].pol);
+}
/**
* Init pwm.
/**
* Init pwm.
@@
-206,10
+234,14
@@
void pwm_hw_init(void)
/*
* Set pwm mode:
* - set period alidned to left
/*
* Set pwm mode:
* - set period alidned to left
- * - set output waveform to
low
level
+ * - set output waveform to
start at high
level
* - allow duty cycle modify at next period event
*/
for (int ch = 0; ch < PWM_CNT; ch++)
* - allow duty cycle modify at next period event
*/
for (int ch = 0; ch < PWM_CNT; ch++)
+ {
*pwm_map[ch].mode_reg = 0;
*pwm_map[ch].mode_reg = 0;
+ *pwm_map[ch].mode_reg = BV(PWM_CPOL);
+ }
+
}
}