+#elif CPU_CM3
+
+ #define CPU_REG_BITS 32
+ #define CPU_REGS_CNT 16
+ #define CPU_HARVARD 0
+
+ /// Valid pointers should be >= than this value (used for debug)
+ #if CPU_CM3_LM3S1968
+ #define CPU_RAM_START 0x20000000
+ #else
+ #warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x200
+ #define CPU_RAM_START 0x200
+ #endif
+
+ #if defined(__ARMEB__)
+ #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+ #elif defined(__ARMEL__)
+ #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #else
+ #error Unable to detect Cortex-M3 endianess!
+ #endif
+
+ #define NOP asm volatile ("nop")
+ #define PAUSE asm volatile ("wfi" ::: "memory")
+ #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
+
+ /*
+ * FIXME: builtin GCC memset() can be buggy! We need to redefine it
+ * here for this architecture. :(
+ */
+ #include <cfg/compiler.h>
+ #define memset __cm3_memset
+ INLINE void *__cm3_memset(void *s, int c, size_t n)
+ {
+ uint8_t *p = (uint8_t *)s;
+
+ while (n--)
+ *p++ = c;
+ return s;
+ }