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Clean up. Add set polarity prototype.
[bertos.git]
/
bertos
/
cpu
/
avr
/
drv
/
adc_avr.c
diff --git
a/bertos/cpu/avr/drv/adc_avr.c
b/bertos/cpu/avr/drv/adc_avr.c
index 33beeca39acad872e9c60739af403f8f3a968472..0aae674332faf44875a6fc7ce9f6aa2a161c294c 100644
(file)
--- a/
bertos/cpu/avr/drv/adc_avr.c
+++ b/
bertos/cpu/avr/drv/adc_avr.c
@@
-37,12
+37,15
@@
* This module is automatically included so no need to include
* in test list.
* notest: avr
* This module is automatically included so no need to include
* in test list.
* notest: avr
+ *
+ * $WIZ$
*/
#include "adc_avr.h"
#include "cfg/cfg_adc.h"
*/
#include "adc_avr.h"
#include "cfg/cfg_adc.h"
-#include "cfg/cfg_kern.h"
+#include "cfg/cfg_proc.h"
+#include "cfg/cfg_signal.h"
#include <cfg/macros.h>
#include <cfg/compiler.h>
#include <cfg/macros.h>
#include <cfg/compiler.h>
@@
-53,9
+56,16
@@
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/io.h>
#include <avr/interrupt.h>
+/**
+ * ADC voltage referencese.
+ *
+ * $WIZ$ avr_adc_refs = "ADC_AVR_AREF", "ADC_AVR_AVCC", "ADC_AVR_INT256"
+ * \{
+ */
#define ADC_AVR_AREF 0
#define ADC_AVR_AVCC 1
#define ADC_AVR_INT256 2
#define ADC_AVR_AREF 0
#define ADC_AVR_AVCC 1
#define ADC_AVR_INT256 2
+/* \} */
#if CONFIG_KERN
#include <cfg/module.h>
#if CONFIG_KERN
#include <cfg/module.h>
@@
-64,7
+74,7
@@
#if !CONFIG_KERN_SIGNALS
#if !CONFIG_KERN_SIGNALS
- #error Signals must be active to use ADC with kernel
+ #error Signals must be active to use
the
ADC with kernel
#endif
/* Signal adc convertion end */
#endif
/* Signal adc convertion end */
@@
-79,7
+89,7
@@
*/
ISR(ADC_vect)
{
*/
ISR(ADC_vect)
{
- sig_
signal
(adc_process, SIG_ADC_COMPLETE);
+ sig_
post
(adc_process, SIG_ADC_COMPLETE);
}
#endif /* CONFIG_KERN */
}
#endif /* CONFIG_KERN */
@@
-87,7
+97,7
@@
* Select mux channel \a ch.
* \todo only first 8 channels are selectable!
*/
* Select mux channel \a ch.
* \todo only first 8 channels are selectable!
*/
-
INLINE
void adc_hw_select_ch(uint8_t ch)
+void adc_hw_select_ch(uint8_t ch)
{
/* Set to 0 all mux registers */
ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
{
/* Set to 0 all mux registers */
ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
@@
-102,7
+112,7
@@
INLINE void adc_hw_select_ch(uint8_t ch)
* If a kernel is present, preempt until convertion is complete, otherwise
* a busy wait on ADCS bit is done.
*/
* If a kernel is present, preempt until convertion is complete, otherwise
* a busy wait on ADCS bit is done.
*/
-
INLINE
uint16_t adc_hw_read(void)
+uint16_t adc_hw_read(void)
{
// Ensure another convertion is not running.
ASSERT(!(ADCSRA & BV(ADSC)));
{
// Ensure another convertion is not running.
ASSERT(!(ADCSRA & BV(ADSC)));
@@
-126,7
+136,7
@@
INLINE uint16_t adc_hw_read(void)
/**
* Init ADC hardware.
*/
/**
* Init ADC hardware.
*/
-
INLINE
void adc_hw_init(void)
+void adc_hw_init(void)
{
/*
* Select channel 0 as default,
{
/*
* Select channel 0 as default,