+#endif /* !CONFIG_I2C_DISABLE_OLD_API */
+
+/*
+ * New Api
+ */
+struct I2cHardware
+{
+};
+
+
+/* Wait for TWINT flag set: bus is ready */
+#define WAIT_READY() \
+ do { \
+ while (!(TWCR & BV(TWINT))) \
+ cpu_relax(); \
+ } while (0)
+
+/**
+ * Send START condition on the bus.
+ */
+INLINE bool i2c_hw_start(void)
+{
+ TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
+ WAIT_READY();
+
+ if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
+ return true;
+
+ return false;
+}
+
+/**
+ * Send STOP condition.
+ */
+INLINE void i2c_hw_stop(void)
+{
+ TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
+}
+
+static void i2c_avr_start(I2c *i2c, uint16_t slave_addr)
+{
+ /*
+ * Loop on the select write sequence: when the eeprom is busy
+ * writing previously sent data it will reply to the SLA_W
+ * control byte with a NACK. In this case, we must
+ * keep trying until the slave responds with an ACK.
+ */
+ ticks_t start = timer_clock();
+ while (i2c_hw_start())
+ {
+ uint8_t sla_ack = 0;
+ uint8_t sla_nack = 0;
+ if (I2C_TEST_START(i2c->flags) == I2C_START_W)
+ {
+ TWDR = slave_addr & ~I2C_READBIT;
+ sla_ack = TW_MT_SLA_ACK;
+ sla_nack = TW_MT_SLA_NACK;
+ }
+ else
+ {
+ TWDR = slave_addr | I2C_READBIT;
+ sla_ack = TW_MR_SLA_ACK;
+ sla_nack = TW_MR_SLA_NACK;
+ }
+
+ TWCR = BV(TWINT) | BV(TWEN);
+ WAIT_READY();
+
+ if (TW_STATUS == sla_ack)
+ return;
+ else if (TW_STATUS != sla_nack)
+ {
+ LOG_ERR("Start addr NACK[%x]\n", TWSR);
+ i2c->errors |= I2C_NO_ACK;
+ i2c_hw_stop();
+ break;
+ }
+ else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
+ {
+ LOG_ERR("Start timeout\n");
+ i2c->errors |= I2C_START_TIMEOUT;
+ i2c_hw_stop();
+ break;
+ }
+ }
+
+ LOG_ERR("I2c error\n");
+ i2c->errors |= I2C_ERR;
+ i2c_hw_stop();
+}
+
+static void i2c_avr_putc(I2c *i2c, const uint8_t data)
+{
+
+ TWDR = data;
+ TWCR = BV(TWINT) | BV(TWEN);
+ WAIT_READY();
+
+ if (TW_STATUS != TW_MT_DATA_ACK)
+ {
+ LOG_ERR("Data nack[%x]\n", TWSR);
+ i2c->errors |= I2C_DATA_NACK;
+ i2c_hw_stop();
+ }
+
+ if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
+ i2c_hw_stop();
+}
+
+static uint8_t i2c_avr_getc(I2c *i2c)
+{
+ uint8_t data_flag = 0;
+ if (i2c->xfer_size == 1)
+ {
+ TWCR = BV(TWINT) | BV(TWEN);
+ data_flag = TW_MR_DATA_NACK;
+ }
+ else
+ {
+ TWCR = BV(TWINT) | BV(TWEN) | BV(TWEA);
+ data_flag = TW_MR_DATA_ACK;
+ }
+
+ WAIT_READY();
+
+ if (TW_STATUS != data_flag)
+ {
+ LOG_ERR("Data nack[%x]\n", TWSR);
+ i2c->errors |= I2C_DATA_NACK;
+ i2c_hw_stop();
+
+ return 0xFF;
+ }
+
+ uint8_t data = TWDR;
+
+ if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
+ i2c_hw_stop();
+
+ return data;
+}
+
+
+static const I2cVT i2c_avr_vt =
+{
+ .start = i2c_avr_start,
+ .getc = i2c_avr_getc,
+ .putc = i2c_avr_putc,
+ .write = i2c_genericWrite,
+ .read = i2c_genericRead,
+};
+
+struct I2cHardware i2c_avr_hw[] =
+{
+ { /* I2C0 */
+ },
+};