+#if AVR_HAS_UART2
+
+/**
+ * Serial 2 RX complete interrupt handler.
+ *
+ * This handler is interruptible.
+ * Interrupt are reenabled as soon as recv complete interrupt is
+ * disabled. Using INTERRUPT() is troublesome when the serial
+ * is heavily loaded, because an interrupt could be retriggered
+ * when executing the handler prologue before RXCIE is disabled.
+ *
+ * \see DECLARE_ISR(USART2_RX_vect)
+ */
+DECLARE_ISR(USART2_RX_vect)
+{
+ SER_STROBE_ON;
+
+ /* Disable Recv complete IRQ */
+ //UCSR1B &= ~BV(RXCIE);
+ //IRQ_ENABLE;
+
+ /* Should be read before UDR */
+ ser_handles[SER_UART2]->status |= UCSR2A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+
+ /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
+ * not going to accept the incoming data
+ */
+ char c = UDR2;
+ struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART2]->rxfifo;
+ //ASSERT_VALID_FIFO(rxfifo);
+
+ if (UNLIKELY(fifo_isfull(rxfifo)))
+ ser_handles[SER_UART2]->status |= SERRF_RXFIFOOVERRUN;
+ else
+ {
+ fifo_push(rxfifo, c);
+#if CONFIG_SER_HWHANDSHAKE
+ if (fifo_isfull(rxfifo))
+ RTS_OFF;
+#endif
+ }
+ /* Re-enable receive complete int */
+ //IRQ_DISABLE;
+ //UCSR1B |= BV(RXCIE);
+
+ SER_STROBE_OFF;
+}
+
+#endif // AVR_HAS_UART2
+
+#if AVR_HAS_UART3
+
+/**
+ * Serial 3 RX complete interrupt handler.
+ *
+ * This handler is interruptible.
+ * Interrupt are reenabled as soon as recv complete interrupt is
+ * disabled. Using INTERRUPT() is troublesome when the serial
+ * is heavily loaded, because an interrupt could be retriggered
+ * when executing the handler prologue before RXCIE is disabled.
+ *
+ * \see DECLARE_ISR(USART3_RX_vect)
+ */
+DECLARE_ISR(USART3_RX_vect)
+{
+ SER_STROBE_ON;
+
+ /* Disable Recv complete IRQ */
+ //UCSR1B &= ~BV(RXCIE);
+ //IRQ_ENABLE;
+
+ /* Should be read before UDR */
+ ser_handles[SER_UART3]->status |= UCSR3A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+
+ /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
+ * not going to accept the incoming data
+ */
+ char c = UDR3;
+ struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART3]->rxfifo;
+ //ASSERT_VALID_FIFO(rxfifo);
+
+ if (UNLIKELY(fifo_isfull(rxfifo)))
+ ser_handles[SER_UART3]->status |= SERRF_RXFIFOOVERRUN;
+ else
+ {
+ fifo_push(rxfifo, c);
+#if CONFIG_SER_HWHANDSHAKE
+ if (fifo_isfull(rxfifo))
+ RTS_OFF;
+#endif
+ }
+ /* Re-enable receive complete int */
+ //IRQ_DISABLE;
+ //UCSR1B |= BV(RXCIE);
+
+ SER_STROBE_OFF;
+}
+
+#endif // AVR_HAS_UART3
+