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at91sam7x: force inlining of all the UART ISR functions.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
clock_lm3s.c
diff --git
a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 1bc63f7ac24fdda41125a8f300c6db4f55d51d06..76e901bda6430b3ca3597de4b2d816fd1258a733 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/
bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@
-51,7
+51,7
@@
/*
* Very small delay: each loop takes 3 cycles.
*/
/*
* Very small delay: each loop takes 3 cycles.
*/
-void NAKED
__delay
(unsigned long iterations)
+void NAKED
lm3s_busyWait
(unsigned long iterations)
{
register uint32_t __n asm("r0") = iterations;
{
register uint32_t __n asm("r0") = iterations;
@@
-113,7
+113,7
@@
void clock_set_rate(void)
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc2;
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc2;
-
__delay
(16);
+
lm3s_busyWait
(16);
/*
* Step #2: select the crystal value (XTAL) and oscillator source
/*
* Step #2: select the crystal value (XTAL) and oscillator source
@@
-139,7
+139,7
@@
void clock_set_rate(void)
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc2;
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc2;
-
__delay
(16);
+
lm3s_busyWait
(16);
/*
* Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
/*
* Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
@@
-171,5
+171,5
@@
void clock_set_rate(void)
HWREG(SYSCTL_RCC) = rcc;
HWREG(SYSCTL_RCC) = rcc;
-
__delay
(16);
+
lm3s_busyWait
(16);
}
}