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sam3n port: add some peripheral register definitions.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
clock_sam3.c
diff --git
a/bertos/cpu/cortex-m3/drv/clock_sam3.c
b/bertos/cpu/cortex-m3/drv/clock_sam3.c
index b0486c51d992ef94edcf16a7e60e4e382ee09a53..25f0f986188be5a812763046453a693b1c7053f6 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/clock_sam3.c
+++ b/
bertos/cpu/cortex-m3/drv/clock_sam3.c
@@
-36,8
+36,7
@@
*/
#include "clock_sam3.h"
*/
#include "clock_sam3.h"
-#include <io/sam3_pmc.h>
-#include <io/sam3_sysctl.h>
+#include <io/sam3.h>
#include <cfg/compiler.h>
#include <cfg/macros.h>
#include <cfg/compiler.h>
#include <cfg/macros.h>
@@
-90,40
+89,46
@@
void clock_init(void)
{
uint32_t timeout;
{
uint32_t timeout;
+ /* Disable watchdog */
+ WDT_MR = WDT_MR_WDDIS;
+
+ /* Set 4 wait states for flash access, needed for higher CPU clock rates */
+ EFC_FMR = EEFC_FMR_FWS(3);
+
// Select external slow clock
// Select external slow clock
- if (!(SUPC_SR
_R
& SUPC_SR_OSCSEL))
+ if (!(SUPC_SR & SUPC_SR_OSCSEL))
{
{
- SUPC_CR
_R
= SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
- while (!(SUPC_SR
_R
& SUPC_SR_OSCSEL));
+ SUPC_CR = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
+ while (!(SUPC_SR & SUPC_SR_OSCSEL));
}
// Initialize main oscillator
}
// Initialize main oscillator
- if (!(
CKGR_MOR_
R & CKGR_MOR_MOSCSEL))
+ if (!(
PMC_MO
R & CKGR_MOR_MOSCSEL))
{
{
-
CKGR_MOR_
R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+
PMC_MO
R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
timeout = CLOCK_TIMEOUT;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR
_R
& PMC_SR_MOSCXTS) && --timeout);
+ while (!(PMC_SR & PMC_SR_MOSCXTS) && --timeout);
}
// Switch to external oscillator
}
// Switch to external oscillator
-
CKGR_MOR_
R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+
PMC_MO
R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
timeout = CLOCK_TIMEOUT;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR
_R
& PMC_SR_MOSCSELS) && --timeout);
+ while (!(PMC_SR & PMC_SR_MOSCSELS) && --timeout);
- PMC_MCKR
_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M
) | PMC_MCKR_CSS_MAIN_CLK;
+ PMC_MCKR
= (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk
) | PMC_MCKR_CSS_MAIN_CLK;
timeout = CLOCK_TIMEOUT;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR
_R
& PMC_SR_MCKRDY) && --timeout);
+ while (!(PMC_SR & PMC_SR_MCKRDY) && --timeout);
// Initialize and enable PLL clock
// Initialize and enable PLL clock
-
CKGR_PLLR_
R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
+
PMC_PLL
R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
timeout = CLOCK_TIMEOUT;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR
_R
& PMC_SR_LOCK) && --timeout);
+ while (!(PMC_SR & PMC_SR_LOCK) && --timeout);
- PMC_MCKR
_R
= PMC_MCKR_CSS_MAIN_CLK;
+ PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
timeout = CLOCK_TIMEOUT;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR
_R
& PMC_SR_MCKRDY) && --timeout);
+ while (!(PMC_SR & PMC_SR_MCKRDY) && --timeout);
- PMC_MCKR
_R
= PMC_MCKR_CSS_PLL_CLK;
+ PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
timeout = CLOCK_TIMEOUT;
timeout = CLOCK_TIMEOUT;
- while (!(PMC_SR
_R
& PMC_SR_MCKRDY) && --timeout);
+ while (!(PMC_SR & PMC_SR_MCKRDY) && --timeout);
}
}