+#include <string.h>
+
+struct DacHardware
+{
+ uint16_t channels;
+ uint32_t rate;
+ bool end;
+};
+
+struct DacHardware dac_hw;
+
+#if CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH0 /* Select Timer counter TIO Channel 0 */
+ #define DAC_TC_ID TC0_ID
+ #define DAC_TC_CCR TC0_CCR0
+ #define DAC_TC_IDR TC0_IDR0
+ #define DAC_TC_CMR TC0_CMR0
+ #define DAC_TC_SR TC0_SR0
+ #define DAC_TC_RA TC0_RA0
+ #define DAC_TC_RC TC0_RC0
+#elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH1 /* Select Timer counter TIO Channel 1 */
+ #define DAC_TC_ID TC1_ID
+ #define DAC_TC_CCR TC0_CCR1
+ #define DAC_TC_IDR TC0_IDR1
+ #define DAC_TC_CMR TC0_CMR1
+ #define DAC_TC_SR TC0_SR1
+ #define DAC_TC_RA TC0_RA1
+ #define DAC_TC_RC TC0_RC1
+#elif CONFIG_DAC_TIMER == DACC_TRGSEL_TIO_CH2 /* Select Timer counter TIO Channel 2 */
+ #define DAC_TC_ID TC2_ID
+ #define DAC_TC_CCR TC0_CCR2
+ #define DAC_TC_IDR TC0_IDR2
+ #define DAC_TC_CMR TC0_CMR2
+ #define DAC_TC_SR TC0_SR2
+ #define DAC_TC_RA TC0_RA2
+ #define DAC_TC_RC TC0_RC2
+#elif CONFIG_DAC_TIMER == DACC_TRGSEL_PWM0 || CONFIG_DAC_TIMER == DACC_TRGSEL_PWM1
+ #error unimplemented pwm triger select.
+#endif
+
+INLINE void tc_setup(uint32_t freq, size_t n_sample)
+{
+ pmc_periphEnable(DAC_TC_ID);
+
+ /* Disable TC clock */
+ DAC_TC_CCR = TC_CCR_CLKDIS;
+ /* Disable interrupts */
+ DAC_TC_IDR = 0xFFFFFFFF;
+ /* Clear status register */
+ volatile uint32_t dummy = DAC_TC_SR;
+ (void)dummy;
+
+ /*
+ * Setup the timer counter:
+ * - select clock TCLK1 (MCK/2)
+ * - enable wave form mode
+ * - RA compare effect SET
+ * - RC compare effect CLEAR
+ * - UP mode with automatic trigger on RC Compare
+ */
+ DAC_TC_CMR = TC_TIMER_CLOCK1 | BV(TC_CMR_WAVE) | TC_CMR_ACPA_SET | TC_CMR_ACPC_CLEAR | BV(TC_CMR_CPCTRG);
+
+ /*
+ * Compute the sample frequency
+ * the RC counter will update every MCK/2 (see above)
+ * so to convert one sample at the user freq we generate
+ * the trigger every TC_CLK / (numer_of_sample * user_freq)
+ * where TC_CLK = MCK / 2.
+ */
+ uint32_t rc = DIV_ROUND((CPU_FREQ / 2), n_sample * freq);
+ DAC_TC_RC = rc;
+ /* generate the square wave with duty = 50% */
+ DAC_TC_RA = DIV_ROUND(50 * rc, 100);
+
+ PIOB_PDR = BV(25);
+ PIO_PERIPH_SEL(PIOB_BASE, BV(25), PIO_PERIPH_B);
+}
+
+INLINE void tc_start(void)
+{
+ DAC_TC_CCR = BV(TC_CCR_CLKEN)| BV(TC_CCR_SWTRG);
+}
+
+INLINE void tc_stop(void)
+{
+ DAC_TC_CCR = BV(TC_CCR_CLKDIS);
+}
+
+static int sam3x_dac_write(struct Dac *dac, unsigned channel, uint16_t sample)
+{
+ (void)dac;
+
+ ASSERT(channel <= DAC_MAXCH);
+
+ DACC_MR |= (channel << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
+ DACC_CHER |= BV(channel);
+
+ DACC_CDR = sample ;
+
+ return 0;
+}
+
+static void sam3x_dac_setCh(struct Dac *dac, uint32_t mask)
+{
+ /* we have only the ch0 and ch1 */
+ ASSERT(mask < BV(3));
+ dac->hw->channels = mask;
+}
+
+static void sam3x_dac_setSampleRate(struct Dac *dac, uint32_t rate)
+{
+ (void)dac;
+
+ /* Eneble hw trigger */
+ DACC_MR |= BV(DACC_TRGEN) | (CONFIG_DAC_TIMER << DACC_TRGSEL_SHIFT);
+ dac->hw->rate = rate;
+}
+
+static void sam3x_dac_conversion(struct Dac *dac, void *buf, size_t len)
+{
+ if (dac->hw->channels & BV(DACC_CH0))
+ DACC_MR |= (DACC_CH0 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
+
+ if (dac->hw->channels & BV(DACC_CH1))
+ DACC_MR |= (DACC_CH1 << DACC_USER_SEL_SHIFT) & DACC_USER_SEL_MASK;
+
+ DACC_CHER |= dac->hw->channels;
+
+ /* setup timer and start it */
+ tc_setup(dac->hw->rate, len);
+ tc_start();
+
+ /* Setup dma and start it */
+ DACC_TPR = (uint32_t)buf ;
+ DACC_TCR = len;
+ DACC_PTCR |= BV(DACC_PTCR_TXTEN);
+}
+
+static bool sam3x_dac_isFinished(struct Dac *dac)