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Manage the page writing on two banks. Move flash info in sam3 defines.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
dmac_sam3.c
diff --git
a/bertos/cpu/cortex-m3/drv/dmac_sam3.c
b/bertos/cpu/cortex-m3/drv/dmac_sam3.c
index 7c5511749f87e2d3ae6f815e111d9a0c8b6e5ca6..06dba6ea9d558b158454a80a8d89b2e567d7c34a 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/dmac_sam3.c
+++ b/
bertos/cpu/cortex-m3/drv/dmac_sam3.c
@@
-109,7
+109,6
@@
struct DmacCh dmac_ch[] =
},
};
},
};
-
/* We use event to signal the end of conversion */
static Dmac dmac[DMAC_CHANNEL_CNT];
static uint8_t dmac_ch_enabled;
/* We use event to signal the end of conversion */
static Dmac dmac[DMAC_CHANNEL_CNT];
static uint8_t dmac_ch_enabled;
@@
-117,6
+116,8
@@
static uint8_t dmac_ch_enabled;
void dmac_setLLITransfer(int ch, DmacDesc *lli, uint32_t cfg)
{
DMAC_CHDR = BV(ch);
void dmac_setLLITransfer(int ch, DmacDesc *lli, uint32_t cfg)
{
DMAC_CHDR = BV(ch);
+ reg32_t reg = DMAC_EBCISR;
+ (void)reg;
*dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
*dmac_ch[ch].desc = (uint32_t)lli;
*dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
*dmac_ch[ch].desc = (uint32_t)lli;
@@
-135,7
+136,7
@@
void dmac_configureDmac(int ch, size_t transfer_size, uint32_t cfg, uint32_t ctr
{
DMAC_CHDR = BV(ch);
{
DMAC_CHDR = BV(ch);
- *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT)
| BV(DMAC_CFG_SOD)
;
+ *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
*dmac_ch[ch].ctrla = ctrla | (transfer_size & DMAC_CTRLA_BTSIZE_MASK);
*dmac_ch[ch].ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
}
*dmac_ch[ch].ctrla = ctrla | (transfer_size & DMAC_CTRLA_BTSIZE_MASK);
*dmac_ch[ch].ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
}
@@
-148,6
+149,7
@@
int dmac_start(int ch)
return -1;
}
DMAC_CHER = BV(ch);
return -1;
}
DMAC_CHER = BV(ch);
+ dmac_ch_enabled |= BV(ch);
return 0;
}
return 0;
}