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Add internal flash driver for sam3x.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
eth_sam3.c
diff --git
a/bertos/cpu/cortex-m3/drv/eth_sam3.c
b/bertos/cpu/cortex-m3/drv/eth_sam3.c
index f83dba7227d71d4ffe551045eb23d82fd2ab6462..f93275db44304e8b66bde6a4cff8bdff6511ed11 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/eth_sam3.c
+++ b/
bertos/cpu/cortex-m3/drv/eth_sam3.c
@@
-234,13
+234,8
@@
static int emac_reset(void)
pmc_periphEnable(PIOD_ID);
pmc_periphEnable(EMAC_ID);
pmc_periphEnable(PIOD_ID);
pmc_periphEnable(EMAC_ID);
- // Disable TESTMODE and RMII
- PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
-
- // Disable PHY power down.
- PIOD_PER = BV(PHY_PWRDN_BIT);
- PIOD_OER = BV(PHY_PWRDN_BIT);
- PIOD_CODR = BV(PHY_PWRDN_BIT);
+ // Disable TESTMODE
+ PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
#endif
// Toggle external hardware reset pin.
#endif
// Toggle external hardware reset pin.
@@
-262,9
+257,6
@@
static int emac_reset(void)
PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
PIOB_PDR = PHY_MII_PINS_PORTB;
PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
PIOB_PDR = PHY_MII_PINS_PORTB;
- PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
- PIOC_PDR = PHY_MII_PINS_PORTC;
-
// Enable receive, transmit clocks and RMII mode.
EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
#endif
// Enable receive, transmit clocks and RMII mode.
EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
#endif