+void hsmci_setBlkSize(size_t blk_size)
+{
+ HSMCI_DMA = BV(HSMCI_DMA_DMAEN);
+ HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT);
+}
+
+bool hsmci_read(uint32_t *buf, size_t word_num)
+{
+ ASSERT(buf);
+ ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
+
+ kprintf("DMAC status %08lx channel st %08lx\n", DMAC_EBCISR, DMAC_CHSR);
+
+ DMAC_SADDR0 = 0x40000200U;
+ DMAC_DADDR0 = (uint32_t)buf;
+ DMAC_DSCR0 = 0;
+
+ DMAC_CTRLA0 = word_num | DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
+ DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
+ DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
+
+ ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
+ DMAC_CHER = BV(DMAC_CHER_ENA0);
+
+ while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
+ cpu_relax();
+
+ DMAC_CHDR = BV(DMAC_CHDR_DIS0);
+ return 0;
+}
+