+void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size)
+{
+ HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
+ HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
+
+ uint32_t cfg = BV(DMAC_CFG_DST_H2SEL);
+ uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
+ uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
+ DMAC_CTRLB_FC_MEM2PER_DMA_FC |
+ DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
+
+ dmac_setSources(&dmac, (uint32_t)buf, (uint32_t)&HSMCI_TDR);
+ dmac_configureDmac(&dmac, word_num, cfg, ctrla, ctrlb);
+ dmac_start(&dmac);
+}
+
+void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size)
+{
+ HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
+ HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
+
+ uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL);
+ uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
+ uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
+ DMAC_CTRLB_FC_PER2MEM_DMA_FC |
+ DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
+
+ dmac_setSources(&dmac, (uint32_t)&HSMCI_RDR, (uint32_t)buf);
+ dmac_configureDmac(&dmac, word_num, cfg, ctrla, ctrlb);
+ dmac_start(&dmac);
+}
+
+
+void hsmci_waitTransfer(void)
+{
+ while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
+ cpu_relax();
+}
+
+void hsmci_setSpeed(uint32_t data_rate, int flag)
+{
+ if (flag & HSMCI_HS_MODE)
+ HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
+ else
+ HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
+
+ HSMCI_MR = HSMCI_CLK_DIV(data_rate) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
+
+ timer_delay(10);
+}
+