+ ASSERT(buf);
+ ASSERT(len >= slice_len);
+ ASSERT(!(len % slice_len));
+
+ i2s->hw->end = false;
+ i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
+
+ sample_buff = (uint8_t *)buf;
+ next_idx = 0;
+ chunk_size = slice_len;
+ remaing_size = len;
+ transfer_size = len;
+
+ memset(&lli0, 0, sizeof(DmacDesc));
+ memset(&lli1, 0, sizeof(DmacDesc));
+
+ prev = 0;
+ curr = &lli1;
+ next = &lli0;
+
+ for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
+ curr->src_addr = (uint32_t)&SSC_RHR;
+ curr->dst_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (chunk_size > remaing_size)
+ break;
+
+ }
+ dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG);
+
+ if (dmac_start(I2S_DMAC_CH) < 0)
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+
+ i2s_status &= ~I2S_STATUS_ERR;
+ i2s_status |= I2S_STATUS_RX;
+
+ SSC_CR = BV(SSC_RXEN) | BV(SSC_TXEN);
+ I2S_STROBE_OFF();
+
+ while (1)
+ {
+ event_wait(&data_ready);
+ if (i2s_status & I2S_STATUS_ERR)
+ {
+ LOG_ERR("Error while streaming.\n");
+ break;
+ }
+
+ if (i2s->hw->end)
+ {
+ LOG_INFO("Stop streaming.\n");
+ break;
+ }
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
+ cpu_relax();
+ }
+}
+
+
+static bool sam3_i2s_isTxFinish(struct I2s *i2s)
+{
+ return i2s->hw->end;
+}
+
+static bool sam3_i2s_isRxFinish(struct I2s *i2s)
+{
+ return i2s->hw->end;
+}
+
+static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
+{
+ (void)i2s;
+ i2s_status |= I2S_STATUS_SINGLE_TRASF;
+
+ dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
+ dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB);
+ dmac_start(I2S_DMAC_CH);
+
+ SSC_CR = BV(SSC_TXEN);
+}
+
+static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len)
+{
+ (void)i2s;
+
+ i2s_status |= I2S_STATUS_SINGLE_TRASF;
+
+ dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
+ dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB);
+ dmac_start(I2S_DMAC_CH);
+
+ SSC_CR = BV(SSC_RXEN);
+}
+
+static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
+{
+ (void)i2s;
+
+ SSC_CR = BV(SSC_TXEN);
+ while(!(SSC_SR & BV(SSC_TXRDY)))
+ cpu_relax();
+
+ SSC_THR = sample;
+ return 0;
+}
+
+static uint32_t sam3_i2s_read(struct I2s *i2s)
+{
+ (void)i2s;
+
+ SSC_CR = BV(SSC_RXEN);
+ while(!(SSC_SR & BV(SSC_RXRDY)))
+ cpu_relax();
+
+ return SSC_RHR;
+}
+
+
+/* We divite for 2 because the min clock for i2s i MCLK/2 */
+#define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
+#define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
+#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
+#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
+#define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
+#define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
+#define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
+
+void i2s_init(I2s *i2s, int channel)
+{
+ (void)channel;
+ i2s->ctx.write = sam3_i2s_write;
+ i2s->ctx.tx_buf = sam3_i2s_txBuf;
+ i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish;
+ i2s->ctx.tx_start = sam3_i2s_txStart;
+ i2s->ctx.tx_wait = sam3_i2s_txWait;
+ i2s->ctx.tx_stop = sam3_i2s_txStop;
+
+ i2s->ctx.read = sam3_i2s_read;
+ i2s->ctx.rx_buf = sam3_i2s_rxBuf;
+ i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish;
+ i2s->ctx.rx_start = sam3_i2s_rxStart;
+ i2s->ctx.rx_wait = sam3_i2s_rxWait;
+ i2s->ctx.rx_stop = sam3_i2s_rxStop;
+
+ DB(i2s->ctx._type = I2S_SAM3X;)
+ i2s->hw = &i2s_hw;
+
+ I2S_STROBE_INIT();
+