+ ASSERT(buf);
+ ASSERT(len >= slice_len);
+ ASSERT(!(len % slice_len));
+
+ i2s->hw->end = false;
+ i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
+
+ sample_buff = (int16_t *)buf;
+ next_idx = 0;
+ chunk_size = slice_len / 2;
+ remaing_size = len / 2;
+ transfer_size = len / 2;
+
+ memset(&lli0, 0, sizeof(DmacDesc));
+ memset(&lli1, 0, sizeof(DmacDesc));
+
+ prev = 0;
+ curr = &lli1;
+ next = &lli0;
+
+ for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
+ curr->src_addr = (uint32_t)&SSC_RHR;
+ curr->dst_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_RX_DMAC_CTRLA | (chunk_size & 0xffff);
+ curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (chunk_size > remaing_size)
+ break;
+
+ }
+ dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG);
+
+ if (dmac_start(I2S_DMAC_CH) < 0)
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+
+ i2s_status &= ~I2S_STATUS_ERR;
+ i2s_status |= I2S_STATUS_RX;
+
+ SSC_CR = BV(SSC_RXEN) | BV(SSC_TXEN);
+ I2S_STROBE_OFF();
+
+ while (1)
+ {
+ event_wait(&data_ready);
+ if (i2s_status & I2S_STATUS_ERR)
+ {
+ LOG_ERR("Error while streaming.\n");
+ break;
+ }
+
+ if (i2s->hw->end)
+ {
+ LOG_INFO("Stop streaming.\n");
+ break;
+ }
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
+ cpu_relax();
+ }