+ dmac_stop(I2S_DMAC_CH);
+
+ next_idx = 0;
+ transfer_size = 0;
+
+ i2s_status |= I2S_STATUS_END_TX;
+ i2s_status &= ~I2S_STATUS_TX;
+ event_do(&data_ready);
+}
+
+static void sam3_i2s_txWait(I2s *i2s)
+{
+ (void)i2s;
+ event_wait(&data_ready);
+}
+
+static void i2s_dmac_irq(uint32_t status)
+{
+ if (i2s_status & I2S_STATUS_SINGLE_TRASF)
+ {
+ i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
+ }
+ else
+ {
+ if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
+ {
+ i2s_status |= I2S_STATUS_ERR;
+ // Disable to reset channel and clear fifo
+ dmac_stop(I2S_DMAC_CH);
+ }
+ else
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ if (i2s_status & I2S_STATUS_TX)
+ {
+ curr->src_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dst_addr = (uint32_t)&SSC_THR;
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+ }
+ else
+ {
+ curr->src_addr = (uint32_t)&SSC_RHR;
+ curr->dst_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+ }
+
+ }
+ }
+ event_do(&data_ready);
+}
+
+
+static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
+{
+ ASSERT(buf);
+ ASSERT(len >= slice_len);
+ ASSERT(!(len % slice_len));
+
+ i2s_status &= ~(I2S_STATUS_END_TX | I2S_STATUS_SINGLE_TRASF);
+
+ sample_buff = (uint8_t *)buf;
+ next_idx = 0;
+ chunk_size = slice_len;
+ size_t remaing_size = len;
+ transfer_size = len;
+
+
+ memset(&lli0, 0, sizeof(DmacDesc));
+ memset(&lli1, 0, sizeof(DmacDesc));
+
+ prev = 0;
+ curr = &lli1;
+ next = &lli0;
+
+ for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
+
+ curr->src_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dst_addr = (uint32_t)&SSC_THR;
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+ }
+
+ dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_TX_DMAC_CFG);
+
+ if (dmac_start(I2S_DMAC_CH) < 0)
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+
+ i2s_status &= ~I2S_STATUS_ERR;
+ i2s_status |= I2S_STATUS_TX;
+
+ SSC_CR = BV(SSC_TXEN);
+
+ while (1)
+ {
+ event_wait(&data_ready);
+ I2S_STROBE_ON();
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+
+ if (i2s_status & I2S_STATUS_ERR)
+ {
+ LOG_ERR("Error while streaming.\n");
+ break;
+ }
+
+ if (i2s_status & I2S_STATUS_END_TX)
+ {
+ LOG_INFO("Stop streaming.\n");
+ break;
+ }
+
+ i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
+ I2S_STROBE_OFF();
+ }
+}
+
+static void sam3_i2s_rxStop(I2s *i2s)
+{
+ (void)i2s;
+ SSC_CR = BV(SSC_RXDIS) | BV(SSC_TXDIS);
+ dmac_stop(I2S_DMAC_CH);
+
+ i2s_status |= I2S_STATUS_END_RX;
+ next_idx = 0;
+ transfer_size = 0;
+
+ i2s_status &= ~I2S_STATUS_RX;
+
+ event_do(&data_ready);
+}
+
+static void sam3_i2s_rxWait(I2s *i2s)
+{
+ (void)i2s;
+ event_wait(&data_ready);
+}
+
+static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
+{
+ ASSERT(buf);
+ ASSERT(len >= slice_len);
+ ASSERT(!(len % slice_len));
+
+ i2s_status &= ~(I2S_STATUS_END_RX | I2S_STATUS_SINGLE_TRASF);
+
+ sample_buff = (uint8_t *)buf;
+ next_idx = 0;
+ chunk_size = slice_len;
+ size_t remaing_size = len;
+ transfer_size = len;
+
+ memset(&lli0, 0, sizeof(DmacDesc));
+ memset(&lli1, 0, sizeof(DmacDesc));
+
+ prev = 0;
+ curr = &lli1;
+ next = &lli0;
+
+ for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ curr->src_addr = (uint32_t)&SSC_RHR;
+ curr->dst_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+ }
+
+ dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG);
+
+ if (dmac_start(I2S_DMAC_CH) < 0)
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+
+ i2s_status &= ~I2S_STATUS_ERR;
+ i2s_status |= I2S_STATUS_RX;
+
+ SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
+
+ while (1)
+ {
+ event_wait(&data_ready);
+ I2S_STROBE_ON();
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+
+ if (i2s_status & I2S_STATUS_ERR)
+ {
+ LOG_ERR("Error while streaming.\n");
+ break;
+ }
+
+ if (i2s_status & I2S_STATUS_END_RX)
+ {
+ LOG_INFO("Stop streaming.\n");
+ break;
+ }
+ I2S_STROBE_OFF();
+ }
+}
+
+
+static bool sam3_i2s_isTxFinish(struct I2s *i2s)
+{
+ (void)i2s;
+ return (i2s_status & I2S_STATUS_END_TX);