+#define I2S_DMAC_CH 0
+#define I2S_CACHED_CHUNK_SIZE 2
+
+
+#define I2S_TX_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (4 & DMAC_CFG_SRC_PER_MASK))
+
+#define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_FIXED | \
+ DMAC_CTRLB_SRC_INCR_INCREMENTING)
+
+
+#define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (4 & DMAC_CFG_SRC_PER_MASK))
+
+#define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_INCREMENTING | \
+ DMAC_CTRLB_SRC_INCR_FIXED)
+
+
+#if CONFIG_WORD_BIT_SIZE == 32
+ #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
+ DMAC_CTRLA_DST_WIDTH_WORD)
+ #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
+ DMAC_CTRLA_DST_WIDTH_WORD)
+ #define I2S_WORD_BYTE_SIZE 4
+#elif CONFIG_WORD_BIT_SIZE == 16
+
+ #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
+ DMAC_CTRLA_DST_WIDTH_HALF_WORD)
+ #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
+ DMAC_CTRLA_DST_WIDTH_HALF_WORD)
+ #define I2S_WORD_BYTE_SIZE 2
+
+#elif CONFIG_WORD_BIT_SIZE == 8
+
+ #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \
+ DMAC_CTRLA_DST_WIDTH_BYTE)
+ #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \
+ DMAC_CTRLA_DST_WIDTH_BYTE)
+ #define I2S_WORD_BYTE_SIZE 1
+
+#else
+ #error Wrong i2s word size.
+#endif
+
+
+#define I2S_STATUS_ERR BV(0)
+#define I2S_STATUS_SINGLE_TRASF BV(1)
+#define I2S_STATUS_TX BV(2)
+#define I2S_STATUS_END_TX BV(3)
+#define I2S_STATUS_RX BV(4)
+#define I2S_STATUS_END_RX BV(5)
+