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CM3: use a distinct stack for handler-mode and thread-mode.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
kdebug_lm3s.c
diff --git
a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index e9061d3618b10df51545c4fc2c9459aa7ca88eeb..7bcfc9ba084bf297110ca4f9f93d60d851501ed3 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/
bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@
-37,6
+37,7
@@
#include <cfg/macros.h> /* for BV() */
#include "kdebug_lm3s.h"
#include <cfg/macros.h> /* for BV() */
#include "kdebug_lm3s.h"
+#include "clock_lm3s.h" /* __delay() */
#include "cfg/cfg_debug.h"
#include "io/lm3s.h"
#include "cfg/cfg_debug.h"
#include "io/lm3s.h"
@@
-123,6
+124,7
@@
INLINE void kdbg_hw_init(void)
/* Enable the peripheral clock */
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
/* Enable the peripheral clock */
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
+ __delay(512);
/* Set GPIO A0 and A1 as UART pins */
HWREG(GPIO_PORTA_BASE + GPIO_O_DIR) |= BV(0) | BV(1);
/* Set GPIO A0 and A1 as UART pins */
HWREG(GPIO_PORTA_BASE + GPIO_O_DIR) |= BV(0) | BV(1);