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We use same gpio port reg.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
ser_stm32.c
diff --git
a/bertos/cpu/cortex-m3/drv/ser_stm32.c
b/bertos/cpu/cortex-m3/drv/ser_stm32.c
index 8a0ae8a31e81abc3e20f9e70dececa0dcbc84106..081a057997ac90e589e145235a630cf282d98b47 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/ser_stm32.c
+++ b/
bertos/cpu/cortex-m3/drv/ser_stm32.c
@@
-149,16
+149,15
@@
void stm32_uartInit(int port)
/* Enable clocking on AFIO */
RCC->APB2ENR |= RCC_APB2_AFIO;
/* Enable clocking on AFIO */
RCC->APB2ENR |= RCC_APB2_AFIO;
+ RCC->APB2ENR |= gpio_uart[port].sysctl;
/* Configure USART pins */
if (port == USART1_PORT)
{
/* Configure USART pins */
if (port == USART1_PORT)
{
- RCC->APB2ENR |= gpio_uart[port].sysctl;
RCC->APB2ENR |= gpio_uart[port].sysctl1;
}
else
{
RCC->APB2ENR |= gpio_uart[port].sysctl1;
}
else
{
- RCC->APB1ENR |= gpio_uart[port].sysctl;
RCC->APB1ENR |= gpio_uart[port].sysctl1;
}
RCC->APB1ENR |= gpio_uart[port].sysctl1;
}