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Add internal flash driver for sam3x.
[bertos.git]
/
bertos
/
cpu
/
cortex-m3
/
drv
/
ser_stm32.c
diff --git
a/bertos/cpu/cortex-m3/drv/ser_stm32.c
b/bertos/cpu/cortex-m3/drv/ser_stm32.c
index 8a0ae8a31e81abc3e20f9e70dececa0dcbc84106..0b8c4f32acfed9162846cd1d52b8d97f00f6d18e 100644
(file)
--- a/
bertos/cpu/cortex-m3/drv/ser_stm32.c
+++ b/
bertos/cpu/cortex-m3/drv/ser_stm32.c
@@
-72,8
+72,8
@@
struct gpio_uart_info
uint32_t rx_pin;
uint32_t tx_pin;
/* Sysctl */
uint32_t rx_pin;
uint32_t tx_pin;
/* Sysctl */
- uint32_t sysctl;
- uint32_t sysctl
1
;
+ uint32_t sysctl
_gpio
;
+ uint32_t sysctl
_usart
;
};
};
@@
-85,25
+85,27
@@
static const struct gpio_uart_info gpio_uart[SER_CNT] =
.base = GPIOA_BASE,
.rx_pin = GPIO_USART1_RX_PIN,
.tx_pin = GPIO_USART1_TX_PIN,
.base = GPIOA_BASE,
.rx_pin = GPIO_USART1_RX_PIN,
.tx_pin = GPIO_USART1_TX_PIN,
- .sysctl = RCC_APB2_GPIOA,
- .sysctl
1
= RCC_APB2_USART1,
+ .sysctl
_gpio
= RCC_APB2_GPIOA,
+ .sysctl
_usart
= RCC_APB2_USART1,
},
/* UART2 */
{
.base = GPIOA_BASE,
.rx_pin = GPIO_USART2_RX_PIN,
.tx_pin = GPIO_USART2_TX_PIN,
},
/* UART2 */
{
.base = GPIOA_BASE,
.rx_pin = GPIO_USART2_RX_PIN,
.tx_pin = GPIO_USART2_TX_PIN,
- .sysctl = RCC_APB2_GPIOA,
- .sysctl
1
= RCC_APB1_USART2,
+ .sysctl
_gpio
= RCC_APB2_GPIOA,
+ .sysctl
_usart
= RCC_APB1_USART2,
},
},
+#if CPU_CM3_STM32F103RB || CPU_CM3_STM32F103RE
/* UART3 */
{
.base = GPIOB_BASE,
.rx_pin = GPIO_USART3_RX_PIN,
.tx_pin = GPIO_USART3_TX_PIN,
/* UART3 */
{
.base = GPIOB_BASE,
.rx_pin = GPIO_USART3_RX_PIN,
.tx_pin = GPIO_USART3_TX_PIN,
- .sysctl = RCC_APB2_GPIOB,
- .sysctl
1
= RCC_APB1_USART3,
+ .sysctl
_gpio
= RCC_APB2_GPIOB,
+ .sysctl
_usart
= RCC_APB1_USART3,
},
},
+#endif
};
#define USART1_PORT 0
};
#define USART1_PORT 0
@@
-149,17
+151,16
@@
void stm32_uartInit(int port)
/* Enable clocking on AFIO */
RCC->APB2ENR |= RCC_APB2_AFIO;
/* Enable clocking on AFIO */
RCC->APB2ENR |= RCC_APB2_AFIO;
+ RCC->APB2ENR |= gpio_uart[port].sysctl_gpio;
/* Configure USART pins */
if (port == USART1_PORT)
{
/* Configure USART pins */
if (port == USART1_PORT)
{
- RCC->APB2ENR |= gpio_uart[port].sysctl;
- RCC->APB2ENR |= gpio_uart[port].sysctl1;
+ RCC->APB2ENR |= gpio_uart[port].sysctl_usart;
}
else
{
}
else
{
- RCC->APB1ENR |= gpio_uart[port].sysctl;
- RCC->APB1ENR |= gpio_uart[port].sysctl1;
+ RCC->APB1ENR |= gpio_uart[port].sysctl_usart;
}
stm32_gpioPinConfig((struct stm32_gpio *)gpio_uart[port].base, gpio_uart[port].tx_pin,
}
stm32_gpioPinConfig((struct stm32_gpio *)gpio_uart[port].base, gpio_uart[port].tx_pin,
@@
-169,9
+170,9
@@
void stm32_uartInit(int port)
GPIO_MODE_IN_FLOATING, GPIO_SPEED_50MHZ);
/* Clear control registry */
GPIO_MODE_IN_FLOATING, GPIO_SPEED_50MHZ);
/* Clear control registry */
- base->CR2 = 0;
//CR2_CLEAR_MASK;
- base->CR1 = 0;
//CR1_CLEAR_MASK;
- base->CR3 = 0;
//CR3_CLEAR_MASK;
+ base->CR2 = 0;
+ base->CR1 = 0;
+ base->CR3 = 0;
base->SR = 0;
/* Set serial param: 115.200 bps, no parity */
base->SR = 0;
/* Set serial param: 115.200 bps, no parity */
@@
-338,7
+339,9
@@
static void stm32_uartIRQDisable(int port)
/* UART port instances */
UART_PORT(1)
UART_PORT(2)
/* UART port instances */
UART_PORT(1)
UART_PORT(2)
+#if CPU_CM3_STM32F103RB || CPU_CM3_STM32F103RE
UART_PORT(3)
UART_PORT(3)
+#endif
static struct CM3Serial UARTDesc[SER_CNT] =
{
static struct CM3Serial UARTDesc[SER_CNT] =
{
@@
-366,6
+369,7
@@
static struct CM3Serial UARTDesc[SER_CNT] =
.base = USART2_BASE,
.irq = USART2_IRQHANDLER,
},
.base = USART2_BASE,
.irq = USART2_IRQHANDLER,
},
+#if CPU_CM3_STM32F103RB || CPU_CM3_STM32F103RE
{
.hw = {
.table = &USART3_VT,
{
.hw = {
.table = &USART3_VT,
@@
-378,6
+382,7
@@
static struct CM3Serial UARTDesc[SER_CNT] =
.base = USART3_BASE,
.irq = USART3_IRQHANDLER,
},
.base = USART3_BASE,
.irq = USART3_IRQHANDLER,
},
+#endif
};
struct SerialHardware *ser_hw_getdesc(int port)
};
struct SerialHardware *ser_hw_getdesc(int port)