+#define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System Clock Enable Register
+#define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System Clock Disable Register
+#define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System Clock Status Register
+#define CKGR_MOR (*((reg32_t *)(PMC_BASE + PMC_MOR_OFF ))) ///< Main Oscillator Register
+#define CKGR_MCFR (*((reg32_t *)(PMC_BASE + PMC_MCFR_OFF))) ///< Main Clock Frequency Register
+#define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master Clock Register
+#define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF ))) ///< Interrupt Enable Register
+#define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF ))) ///< Interrupt Disable Register
+#define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF ))) ///< Status Register
+#define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF ))) ///< Interrupt Mask Register
+#define PMC_FSMR (*((reg32_t *)(PMC_BASE + PMC_FSMR_OFF))) ///< Fast Startup Mode Register
+#define PMC_FSPR (*((reg32_t *)(PMC_BASE + PMC_FSPR_OFF))) ///< Fast Startup Polarity Register
+#define PMC_FOCR (*((reg32_t *)(PMC_BASE + PMC_FOCR_OFF))) ///< Fault Output Clear Register
+#define PMC_WPMR (*((reg32_t *)(PMC_BASE + PMC_WPMR_OFF))) ///< Write Protect Mode Register
+#define PMC_WPSR (*((reg32_t *)(PMC_BASE + PMC_WPSR_OFF))) ///< Write Protect Status Register
+
+#if CPU_CM3_SAM3N
+ #define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral Clock Enable Register
+ #define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral Clock Disable Register
+ #define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral Clock Status Register
+ #define CKGR_PLLR (*((reg32_t *)(PMC_BASE + PMC_PLLR_OFF))) ///< PLL Register
+ #define PMC_PCK (*((reg32_t *)(PMC_BASE + PMC_PCK_OFF ))) ///< Programmable Clock 0 Register
+ #define PMC_OCR (*((reg32_t *)(PMC_BASE + PMC_OCR_OFF ))) ///< Oscillator Calibration Register
+#elif CPU_CM3_SAM3X
+ #define PMC_PCER0 (*((reg32_t *)(PMC_BASE + PMC_PCER0_OFF))) ///< Peripheral Clock Enable Register
+ #define PMC_PCDR0 (*((reg32_t *)(PMC_BASE + PMC_PCDR0_OFF))) ///< Peripheral Clock Disable Register
+ #define PMC_PCSR0 (*((reg32_t *)(PMC_BASE + PMC_PCSR0_OFF))) ///< Peripheral Clock Status Register
+ #define PMC_UCKR (*((reg32_t *)(PMC_BASE + PMC_UCKR _OFF))) ///< UTMI clock register
+ #define CKGR_PLLAR (*((reg32_t *)(PMC_BASE + PMC_PLLAR_OFF))) ///< PLL Register
+ #define PMC_USB_O (*((reg32_t *)(PMC_BASE + PMC_USB_O_OFF))) ///< USB clock register
+ #define PMC_PCK0 (*((reg32_t *)(PMC_BASE + PMC_PCK0 _OFF))) ///< Programmable Clock 0 Register
+ #define PMC_PCK1 (*((reg32_t *)(PMC_BASE + PMC_PCK1 _OFF))) ///< Programmable Clock 1 Register
+ #define PMC_PCK2 (*((reg32_t *)(PMC_BASE + PMC_PCK2 _OFF))) ///< Programmable Clock 2 Register
+ #define PMC_PCER1 (*((reg32_t *)(PMC_BASE + PMC_PCER1_OFF))) ///< Peripheral Clock Enable Register
+ #define PMC_PCDR1 (*((reg32_t *)(PMC_BASE + PMC_PCDR1_OFF))) ///< Peripheral Clock Disable Register
+ #define PMC_PCSR1 (*((reg32_t *)(PMC_BASE + PMC_PCSR1_OFF))) ///< Peripheral Clock Status Register
+ #define PMC_PCR (*((reg32_t *)(PMC_BASE + PMC_PCR _OFF))) ///< Oscillator Calibration Register
+
+ #define CKGR_PLLR CKGR_PLLAR
+#endif