-#define PMC_PCDR_PID2 BV(2) ///< Peripheral Clock 2 Disable
-#define PMC_PCDR_PID3 BV(3) ///< Peripheral Clock 3 Disable
-#define PMC_PCDR_PID4 BV(4) ///< Peripheral Clock 4 Disable
-#define PMC_PCDR_PID5 BV(5) ///< Peripheral Clock 5 Disable
-#define PMC_PCDR_PID6 BV(6) ///< Peripheral Clock 6 Disable
-#define PMC_PCDR_PID7 BV(7) ///< Peripheral Clock 7 Disable
-#define PMC_PCDR_PID8 BV(8) ///< Peripheral Clock 8 Disable
-#define PMC_PCDR_PID9 BV(9) ///< Peripheral Clock 9 Disable
-#define PMC_PCDR_PID10 BV(10) ///< Peripheral Clock 10 Disable
-#define PMC_PCDR_PID11 BV(11) ///< Peripheral Clock 11 Disable
-#define PMC_PCDR_PID12 BV(12) ///< Peripheral Clock 12 Disable
-#define PMC_PCDR_PID13 BV(13) ///< Peripheral Clock 13 Disable
-#define PMC_PCDR_PID14 BV(14) ///< Peripheral Clock 14 Disable
-#define PMC_PCDR_PID15 BV(15) ///< Peripheral Clock 15 Disable
-#define PMC_PCDR_PID16 BV(16) ///< Peripheral Clock 16 Disable
-#define PMC_PCDR_PID17 BV(17) ///< Peripheral Clock 17 Disable
-#define PMC_PCDR_PID18 BV(18) ///< Peripheral Clock 18 Disable
-#define PMC_PCDR_PID19 BV(19) ///< Peripheral Clock 19 Disable
-#define PMC_PCDR_PID20 BV(20) ///< Peripheral Clock 20 Disable
-#define PMC_PCDR_PID21 BV(21) ///< Peripheral Clock 21 Disable
-#define PMC_PCDR_PID22 BV(22) ///< Peripheral Clock 22 Disable
-#define PMC_PCDR_PID23 BV(23) ///< Peripheral Clock 23 Disable
-#define PMC_PCDR_PID24 BV(24) ///< Peripheral Clock 24 Disable
-#define PMC_PCDR_PID25 BV(25) ///< Peripheral Clock 25 Disable
-#define PMC_PCDR_PID26 BV(26) ///< Peripheral Clock 26 Disable
-#define PMC_PCDR_PID27 BV(27) ///< Peripheral Clock 27 Disable
-#define PMC_PCDR_PID28 BV(28) ///< Peripheral Clock 28 Disable
-#define PMC_PCDR_PID29 BV(29) ///< Peripheral Clock 29 Disable
-#define PMC_PCDR_PID30 BV(30) ///< Peripheral Clock 30 Disable
-#define PMC_PCDR_PID31 BV(31) ///< Peripheral Clock 31 Disable
+#define PMC_PCDR_PID2 2 ///< Peripheral Clock 2 Disable
+#define PMC_PCDR_PID3 3 ///< Peripheral Clock 3 Disable
+#define PMC_PCDR_PID4 4 ///< Peripheral Clock 4 Disable
+#define PMC_PCDR_PID5 5 ///< Peripheral Clock 5 Disable
+#define PMC_PCDR_PID6 6 ///< Peripheral Clock 6 Disable
+#define PMC_PCDR_PID7 7 ///< Peripheral Clock 7 Disable
+#define PMC_PCDR_PID8 8 ///< Peripheral Clock 8 Disable
+#define PMC_PCDR_PID9 9 ///< Peripheral Clock 9 Disable
+#define PMC_PCDR_PID10 10 ///< Peripheral Clock 10 Disable
+#define PMC_PCDR_PID11 11 ///< Peripheral Clock 11 Disable
+#define PMC_PCDR_PID12 12 ///< Peripheral Clock 12 Disable
+#define PMC_PCDR_PID13 13 ///< Peripheral Clock 13 Disable
+#define PMC_PCDR_PID14 14 ///< Peripheral Clock 14 Disable
+#define PMC_PCDR_PID15 15 ///< Peripheral Clock 15 Disable
+#define PMC_PCDR_PID16 16 ///< Peripheral Clock 16 Disable
+#define PMC_PCDR_PID17 17 ///< Peripheral Clock 17 Disable
+#define PMC_PCDR_PID18 18 ///< Peripheral Clock 18 Disable
+#define PMC_PCDR_PID19 19 ///< Peripheral Clock 19 Disable
+#define PMC_PCDR_PID20 20 ///< Peripheral Clock 20 Disable
+#define PMC_PCDR_PID21 21 ///< Peripheral Clock 21 Disable
+#define PMC_PCDR_PID22 22 ///< Peripheral Clock 22 Disable
+#define PMC_PCDR_PID23 23 ///< Peripheral Clock 23 Disable
+#define PMC_PCDR_PID24 24 ///< Peripheral Clock 24 Disable
+#define PMC_PCDR_PID25 25 ///< Peripheral Clock 25 Disable
+#define PMC_PCDR_PID26 26 ///< Peripheral Clock 26 Disable
+#define PMC_PCDR_PID27 27 ///< Peripheral Clock 27 Disable
+#define PMC_PCDR_PID28 28 ///< Peripheral Clock 28 Disable
+#define PMC_PCDR_PID29 29 ///< Peripheral Clock 29 Disable
+#define PMC_PCDR_PID30 30 ///< Peripheral Clock 30 Disable
+#define PMC_PCDR_PID31 31 ///< Peripheral Clock 31 Disable