+/**
+ * UART register addresses.
+ */
+/*\{*/
+#if defined(UART0_BASE)
+ #define UART0_ACCESS(offset) (*((reg32_t *)(UART0_BASE + (offset))))
+
+ #define UART_CR UART0_ACCESS(UART_CR_OFF) //< Control Register
+ #define UART_MR UART0_ACCESS(UART_MR_OFF) //< Mode Register
+ #define UART_IER UART0_ACCESS(UART_IER_OFF) //< Interrupt Enable Register
+ #define UART_IDR UART0_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register
+ #define UART_IMR UART0_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register
+ #define UART_SR UART0_ACCESS(UART_SR_OFF) //< Status Register
+ #define UART_RHR UART0_ACCESS(UART_RHR_OFF) //< Receive Holding Register
+ #define UART_THR UART0_ACCESS(UART_THR_OFF) //< Transmit Holding Register
+ #define UART_BRGR UART0_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register
+
+ #define UART_RPR UART0_ACCESS(UART_RPR_OFF) //< Receive Pointer Register
+ #define UART_RCR UART0_ACCESS(UART_RCR_OFF) //< Receive Counter Register
+ #define UART_TPR UART0_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register
+ #define UART_TCR UART0_ACCESS(UART_TCR_OFF) //< Transmit Counter Register
+ #define UART_RNPR UART0_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register
+ #define UART_RNCR UART0_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register
+ #define UART_TNPR UART0_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register
+ #define UART_TNCR UART0_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register
+ #define UART_PTCR UART0_ACCESS(UART_PTCR_OFF) //< Transfer Control Register
+ #define UART_PTSR UART0_ACCESS(UART_PTSR_OFF) //< Transfer Status Register
+#endif /* UART0_BASE */
+
+#if defined(UART1_BASE)
+ #define UART1_ACCESS(offset) (*((reg32_t *)(UART1_BASE + (offset))))
+
+ #define UART_CR UART1_ACCESS(UART_CR_OFF) //< Control Register
+ #define UART_MR UART1_ACCESS(UART_MR_OFF) //< Mode Register
+ #define UART_IER UART1_ACCESS(UART_IER_OFF) //< Interrupt Enable Register
+ #define UART_IDR UART1_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register
+ #define UART_IMR UART1_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register
+ #define UART_SR UART1_ACCESS(UART_SR_OFF) //< Status Register
+ #define UART_RHR UART1_ACCESS(UART_RHR_OFF) //< Receive Holding Register
+ #define UART_THR UART1_ACCESS(UART_THR_OFF) //< Transmit Holding Register
+ #define UART_BRGR UART1_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register
+
+ #define UART_RPR UART1_ACCESS(UART_RPR_OFF) //< Receive Pointer Register
+ #define UART_RCR UART1_ACCESS(UART_RCR_OFF) //< Receive Counter Register
+ #define UART_TPR UART1_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register
+ #define UART_TCR UART1_ACCESS(UART_TCR_OFF) //< Transmit Counter Register
+ #define UART_RNPR UART1_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register
+ #define UART_RNCR UART1_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register
+ #define UART_TNPR UART1_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register
+ #define UART_TNCR UART1_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register
+ #define UART_PTCR UART1_ACCESS(UART_PTCR_OFF) //< Transfer Control Register
+ #define UART_PTSR UART1_ACCESS(UART_PTSR_OFF) //< Transfer Status Register
+#endif /* UART0_BASE */
+/*\}*/