-#include <io/cm3_types.h>
-#include <io/stm32_memmap.h>
-
-/**
- * The following are defines for the fault assignments.
- */
-/*\{*/
-#define FAULT_NMI 2 ///< NMI fault
-#define FAULT_HARD 3 ///< Hard fault
-#define FAULT_MPU 4 ///< MPU fault
-#define FAULT_BUS 5 ///< Bus fault
-#define FAULT_USAGE 6 ///< Usage fault
-#define FAULT_SVCALL 11 ///< SVCall
-#define FAULT_DEBUG 12 ///< Debug monitor
-#define FAULT_PENDSV 14 ///< PendSV
-#define FAULT_SYSTICK 15 ///< System Tick
-/*\}*/
-
-/**
- * The following are defines for the total number of interrupts.
- */
-/*\{*/
-#define NUM_INTERRUPTS 71
-/*\}*/
-
-/**
- * NVIC registers (NVIC)
- */
-/*\{*/
-#define NVIC_INT_TYPE_R (*((reg32_t *)0xE000E004))
-#define NVIC_ST_CTRL_R (*((reg32_t *)0xE000E010))
-#define NVIC_ST_RELOAD_R (*((reg32_t *)0xE000E014))
-#define NVIC_ST_CURRENT_R (*((reg32_t *)0xE000E018))
-#define NVIC_ST_CAL_R (*((reg32_t *)0xE000E01C))
-#define NVIC_EN0_R (*((reg32_t *)0xE000E100))
-#define NVIC_EN1_R (*((reg32_t *)0xE000E104))
-#define NVIC_DIS0_R (*((reg32_t *)0xE000E180))
-#define NVIC_DIS1_R (*((reg32_t *)0xE000E184))
-#define NVIC_PEND0_R (*((reg32_t *)0xE000E200))
-#define NVIC_PEND1_R (*((reg32_t *)0xE000E204))
-#define NVIC_UNPEND0_R (*((reg32_t *)0xE000E280))
-#define NVIC_UNPEND1_R (*((reg32_t *)0xE000E284))
-#define NVIC_ACTIVE0_R (*((reg32_t *)0xE000E300))
-#define NVIC_ACTIVE1_R (*((reg32_t *)0xE000E304))
-#define NVIC_PRI0_R (*((reg32_t *)0xE000E400))
-#define NVIC_PRI1_R (*((reg32_t *)0xE000E404))
-#define NVIC_PRI2_R (*((reg32_t *)0xE000E408))
-#define NVIC_PRI3_R (*((reg32_t *)0xE000E40C))
-#define NVIC_PRI4_R (*((reg32_t *)0xE000E410))
-#define NVIC_PRI5_R (*((reg32_t *)0xE000E414))
-#define NVIC_PRI6_R (*((reg32_t *)0xE000E418))
-#define NVIC_PRI7_R (*((reg32_t *)0xE000E41C))
-#define NVIC_PRI8_R (*((reg32_t *)0xE000E420))
-#define NVIC_PRI9_R (*((reg32_t *)0xE000E424))
-#define NVIC_PRI10_R (*((reg32_t *)0xE000E428))
-#define NVIC_CPUID_R (*((reg32_t *)0xE000ED00))
-#define NVIC_INT_CTRL_R (*((reg32_t *)0xE000ED04))
-#define NVIC_VTABLE_R (*((reg32_t *)0xE000ED08))
-#define NVIC_APINT_R (*((reg32_t *)0xE000ED0C))
-#define NVIC_SYS_CTRL_R (*((reg32_t *)0xE000ED10))
-#define NVIC_CFG_CTRL_R (*((reg32_t *)0xE000ED14))
-#define NVIC_SYS_PRI1_R (*((reg32_t *)0xE000ED18))
-#define NVIC_SYS_PRI2_R (*((reg32_t *)0xE000ED1C))
-#define NVIC_SYS_PRI3_R (*((reg32_t *)0xE000ED20))
-#define NVIC_SYS_HND_CTRL_R (*((reg32_t *)0xE000ED24))
-#define NVIC_FAULT_STAT_R (*((reg32_t *)0xE000ED28))
-#define NVIC_HFAULT_STAT_R (*((reg32_t *)0xE000ED2C))
-#define NVIC_DEBUG_STAT_R (*((reg32_t *)0xE000ED30))
-#define NVIC_MM_ADDR_R (*((reg32_t *)0xE000ED34))
-#define NVIC_FAULT_ADDR_R (*((reg32_t *)0xE000ED38))
-#define NVIC_MPU_TYPE_R (*((reg32_t *)0xE000ED90))
-#define NVIC_MPU_CTRL_R (*((reg32_t *)0xE000ED94))
-#define NVIC_MPU_NUMBER_R (*((reg32_t *)0xE000ED98))
-#define NVIC_MPU_BASE_R (*((reg32_t *)0xE000ED9C))
-#define NVIC_MPU_ATTR_R (*((reg32_t *)0xE000EDA0))
-#define NVIC_DBG_CTRL_R (*((reg32_t *)0xE000EDF0))
-#define NVIC_DBG_XFER_R (*((reg32_t *)0xE000EDF4))
-#define NVIC_DBG_DATA_R (*((reg32_t *)0xE000EDF8))
-#define NVIC_DBG_INT_R (*((reg32_t *)0xE000EDFC))
-#define NVIC_SW_TRIG_R (*((reg32_t *)0xE000EF00))
-/*\}*/
-
-/**
- * The following are defines for the NVIC register addresses.
- */
-/*\{*/
-#define NVIC_INT_TYPE 0xE000E004 ///< Interrupt Controller Type Reg
-#define NVIC_ST_CTRL 0xE000E010 ///< SysTick Control and Status Reg
-#define NVIC_ST_RELOAD 0xE000E014 ///< SysTick Reload Value Register
-#define NVIC_ST_CURRENT 0xE000E018 ///< SysTick Current Value Register
-#define NVIC_ST_CAL 0xE000E01C ///< SysTick Calibration Value Reg
-#define NVIC_EN0 0xE000E100 ///< IRQ 0 to 31 Set Enable Register
-#define NVIC_EN1 0xE000E104 ///< IRQ 32 to 63 Set Enable Register
-#define NVIC_DIS0 0xE000E180 ///< IRQ 0 to 31 Clear Enable Reg
-#define NVIC_DIS1 0xE000E184 ///< IRQ 32 to 63 Clear Enable Reg
-#define NVIC_PEND0 0xE000E200 ///< IRQ 0 to 31 Set Pending Register
-#define NVIC_PEND1 0xE000E204 ///< IRQ 32 to 63 Set Pending Reg
-#define NVIC_UNPEND0 0xE000E280 ///< IRQ 0 to 31 Clear Pending Reg
-#define NVIC_UNPEND1 0xE000E284 ///< IRQ 32 to 63 Clear Pending Reg
-#define NVIC_ACTIVE0 0xE000E300 ///< IRQ 0 to 31 Active Register
-#define NVIC_ACTIVE1 0xE000E304 ///< IRQ 32 to 63 Active Register
-#define NVIC_PRI0 0xE000E400 ///< IRQ 0 to 3 Priority Register
-#define NVIC_PRI1 0xE000E404 ///< IRQ 4 to 7 Priority Register
-#define NVIC_PRI2 0xE000E408 ///< IRQ 8 to 11 Priority Register
-#define NVIC_PRI3 0xE000E40C ///< IRQ 12 to 15 Priority Register
-#define NVIC_PRI4 0xE000E410 ///< IRQ 16 to 19 Priority Register
-#define NVIC_PRI5 0xE000E414 ///< IRQ 20 to 23 Priority Register
-#define NVIC_PRI6 0xE000E418 ///< IRQ 24 to 27 Priority Register
-#define NVIC_PRI7 0xE000E41C ///< IRQ 28 to 31 Priority Register
-#define NVIC_PRI8 0xE000E420 ///< IRQ 32 to 35 Priority Register
-#define NVIC_PRI9 0xE000E424 ///< IRQ 36 to 39 Priority Register
-#define NVIC_PRI10 0xE000E428 ///< IRQ 40 to 43 Priority Register
-#define NVIC_PRI11 0xE000E42C ///< IRQ 44 to 47 Priority Register
-#define NVIC_PRI12 0xE000E430 ///< IRQ 48 to 51 Priority Register
-#define NVIC_PRI13 0xE000E434 ///< IRQ 52 to 55 Priority Register
-#define NVIC_CPUID 0xE000ED00 ///< CPUID Base Register
-#define NVIC_INT_CTRL 0xE000ED04 ///< Interrupt Control State Register
-#define NVIC_VTABLE 0xE000ED08 ///< Vector Table Offset Register
-#define NVIC_APINT 0xE000ED0C ///< App. Int & Reset Control Reg
-#define NVIC_SYS_CTRL 0xE000ED10 ///< System Control Register
-#define NVIC_CFG_CTRL 0xE000ED14 ///< Configuration Control Register
-#define NVIC_SYS_PRI1 0xE000ED18 ///< Sys. Handlers 4 to 7 Priority
-#define NVIC_SYS_PRI2 0xE000ED1C ///< Sys. Handlers 8 to 11 Priority
-#define NVIC_SYS_PRI3 0xE000ED20 ///< Sys. Handlers 12 to 15 Priority
-#define NVIC_SYS_HND_CTRL 0xE000ED24 ///< System Handler Control and State
-#define NVIC_FAULT_STAT 0xE000ED28 ///< Configurable Fault Status Reg
-#define NVIC_HFAULT_STAT 0xE000ED2C ///< Hard Fault Status Register
-#define NVIC_DEBUG_STAT 0xE000ED30 ///< Debug Status Register
-#define NVIC_MM_ADDR 0xE000ED34 ///< Mem Manage Address Register
-#define NVIC_FAULT_ADDR 0xE000ED38 ///< Bus Fault Address Register
-#define NVIC_MPU_TYPE 0xE000ED90 ///< MPU Type Register
-#define NVIC_MPU_CTRL 0xE000ED94 ///< MPU Control Register
-#define NVIC_MPU_NUMBER 0xE000ED98 ///< MPU Region Number Register
-#define NVIC_MPU_BASE 0xE000ED9C ///< MPU Region Base Address Register
-#define NVIC_MPU_ATTR 0xE000EDA0 ///< MPU Region Attribute & Size Reg
-#define NVIC_DBG_CTRL 0xE000EDF0 ///< Debug Control and Status Reg
-#define NVIC_DBG_XFER 0xE000EDF4 ///< Debug Core Reg. Transfer Select
-#define NVIC_DBG_DATA 0xE000EDF8 ///< Debug Core Register Data
-#define NVIC_DBG_INT 0xE000EDFC ///< Debug Reset Interrupt Control
-#define NVIC_SW_TRIG 0xE000EF00 ///< Software Trigger Interrupt Reg
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_INT_TYPE register.
- */
-/*\{*/
-#define NVIC_INT_TYPE_LINES_M 0x0000001F ///< Number of interrupt lines (x32)
-#define NVIC_INT_TYPE_LINES_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_ST_CTRL register.
- */
-/*\{*/
-#define NVIC_ST_CTRL_COUNT 0x00010000 ///< Count flag
-#define NVIC_ST_CTRL_CLK_SRC 0x00000004 ///< Clock Source
-#define NVIC_ST_CTRL_INTEN 0x00000002 ///< Interrupt enable
-#define NVIC_ST_CTRL_ENABLE 0x00000001 ///< Counter mode
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_ST_RELOAD register.
- */
-/*\{*/
-#define NVIC_ST_RELOAD_M 0x00FFFFFF ///< Counter load value
-#define NVIC_ST_RELOAD_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_ST_CURRENT
-* register.
- */
-/*\{*/
-#define NVIC_ST_CURRENT_M 0x00FFFFFF ///< Counter current value
-#define NVIC_ST_CURRENT_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_ST_CAL register.
- */
-/*\{*/
-#define NVIC_ST_CAL_NOREF 0x80000000 ///< No reference clock
-#define NVIC_ST_CAL_SKEW 0x40000000 ///< Clock skew
-#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF ///< 1ms reference value
-#define NVIC_ST_CAL_ONEMS_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_EN0 register.
- */
-/*\{*/
-#define NVIC_EN0_INT31 0x80000000 ///< Interrupt 31 enable
-#define NVIC_EN0_INT30 0x40000000 ///< Interrupt 30 enable
-#define NVIC_EN0_INT29 0x20000000 ///< Interrupt 29 enable
-#define NVIC_EN0_INT28 0x10000000 ///< Interrupt 28 enable
-#define NVIC_EN0_INT27 0x08000000 ///< Interrupt 27 enable
-#define NVIC_EN0_INT26 0x04000000 ///< Interrupt 26 enable
-#define NVIC_EN0_INT25 0x02000000 ///< Interrupt 25 enable
-#define NVIC_EN0_INT24 0x01000000 ///< Interrupt 24 enable
-#define NVIC_EN0_INT23 0x00800000 ///< Interrupt 23 enable
-#define NVIC_EN0_INT22 0x00400000 ///< Interrupt 22 enable
-#define NVIC_EN0_INT21 0x00200000 ///< Interrupt 21 enable
-#define NVIC_EN0_INT20 0x00100000 ///< Interrupt 20 enable
-#define NVIC_EN0_INT19 0x00080000 ///< Interrupt 19 enable
-#define NVIC_EN0_INT18 0x00040000 ///< Interrupt 18 enable
-#define NVIC_EN0_INT17 0x00020000 ///< Interrupt 17 enable
-#define NVIC_EN0_INT16 0x00010000 ///< Interrupt 16 enable
-#define NVIC_EN0_INT15 0x00008000 ///< Interrupt 15 enable
-#define NVIC_EN0_INT14 0x00004000 ///< Interrupt 14 enable
-#define NVIC_EN0_INT13 0x00002000 ///< Interrupt 13 enable
-#define NVIC_EN0_INT12 0x00001000 ///< Interrupt 12 enable
-#define NVIC_EN0_INT11 0x00000800 ///< Interrupt 11 enable
-#define NVIC_EN0_INT10 0x00000400 ///< Interrupt 10 enable
-#define NVIC_EN0_INT9 0x00000200 ///< Interrupt 9 enable
-#define NVIC_EN0_INT8 0x00000100 ///< Interrupt 8 enable
-#define NVIC_EN0_INT7 0x00000080 ///< Interrupt 7 enable
-#define NVIC_EN0_INT6 0x00000040 ///< Interrupt 6 enable
-#define NVIC_EN0_INT5 0x00000020 ///< Interrupt 5 enable
-#define NVIC_EN0_INT4 0x00000010 ///< Interrupt 4 enable
-#define NVIC_EN0_INT3 0x00000008 ///< Interrupt 3 enable
-#define NVIC_EN0_INT2 0x00000004 ///< Interrupt 2 enable
-#define NVIC_EN0_INT1 0x00000002 ///< Interrupt 1 enable
-#define NVIC_EN0_INT0 0x00000001 ///< Interrupt 0 enable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_EN1 register.
- */
-/*\{*/
-#define NVIC_EN1_INT59 0x08000000 ///< Interrupt 59 enable
-#define NVIC_EN1_INT58 0x04000000 ///< Interrupt 58 enable
-#define NVIC_EN1_INT57 0x02000000 ///< Interrupt 57 enable
-#define NVIC_EN1_INT56 0x01000000 ///< Interrupt 56 enable
-#define NVIC_EN1_INT55 0x00800000 ///< Interrupt 55 enable
-#define NVIC_EN1_INT54 0x00400000 ///< Interrupt 54 enable
-#define NVIC_EN1_INT53 0x00200000 ///< Interrupt 53 enable
-#define NVIC_EN1_INT52 0x00100000 ///< Interrupt 52 enable
-#define NVIC_EN1_INT51 0x00080000 ///< Interrupt 51 enable
-#define NVIC_EN1_INT50 0x00040000 ///< Interrupt 50 enable
-#define NVIC_EN1_INT49 0x00020000 ///< Interrupt 49 enable
-#define NVIC_EN1_INT48 0x00010000 ///< Interrupt 48 enable
-#define NVIC_EN1_INT47 0x00008000 ///< Interrupt 47 enable
-#define NVIC_EN1_INT46 0x00004000 ///< Interrupt 46 enable
-#define NVIC_EN1_INT45 0x00002000 ///< Interrupt 45 enable
-#define NVIC_EN1_INT44 0x00001000 ///< Interrupt 44 enable
-#define NVIC_EN1_INT43 0x00000800 ///< Interrupt 43 enable
-#define NVIC_EN1_INT42 0x00000400 ///< Interrupt 42 enable
-#define NVIC_EN1_INT41 0x00000200 ///< Interrupt 41 enable
-#define NVIC_EN1_INT40 0x00000100 ///< Interrupt 40 enable
-#define NVIC_EN1_INT39 0x00000080 ///< Interrupt 39 enable
-#define NVIC_EN1_INT38 0x00000040 ///< Interrupt 38 enable
-#define NVIC_EN1_INT37 0x00000020 ///< Interrupt 37 enable
-#define NVIC_EN1_INT36 0x00000010 ///< Interrupt 36 enable
-#define NVIC_EN1_INT35 0x00000008 ///< Interrupt 35 enable
-#define NVIC_EN1_INT34 0x00000004 ///< Interrupt 34 enable
-#define NVIC_EN1_INT33 0x00000002 ///< Interrupt 33 enable
-#define NVIC_EN1_INT32 0x00000001 ///< Interrupt 32 enable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DIS0 register.
- */
-/*\{*/
-#define NVIC_DIS0_INT31 0x80000000 ///< Interrupt 31 disable
-#define NVIC_DIS0_INT30 0x40000000 ///< Interrupt 30 disable
-#define NVIC_DIS0_INT29 0x20000000 ///< Interrupt 29 disable
-#define NVIC_DIS0_INT28 0x10000000 ///< Interrupt 28 disable
-#define NVIC_DIS0_INT27 0x08000000 ///< Interrupt 27 disable
-#define NVIC_DIS0_INT26 0x04000000 ///< Interrupt 26 disable
-#define NVIC_DIS0_INT25 0x02000000 ///< Interrupt 25 disable
-#define NVIC_DIS0_INT24 0x01000000 ///< Interrupt 24 disable
-#define NVIC_DIS0_INT23 0x00800000 ///< Interrupt 23 disable
-#define NVIC_DIS0_INT22 0x00400000 ///< Interrupt 22 disable
-#define NVIC_DIS0_INT21 0x00200000 ///< Interrupt 21 disable
-#define NVIC_DIS0_INT20 0x00100000 ///< Interrupt 20 disable
-#define NVIC_DIS0_INT19 0x00080000 ///< Interrupt 19 disable
-#define NVIC_DIS0_INT18 0x00040000 ///< Interrupt 18 disable
-#define NVIC_DIS0_INT17 0x00020000 ///< Interrupt 17 disable
-#define NVIC_DIS0_INT16 0x00010000 ///< Interrupt 16 disable
-#define NVIC_DIS0_INT15 0x00008000 ///< Interrupt 15 disable
-#define NVIC_DIS0_INT14 0x00004000 ///< Interrupt 14 disable
-#define NVIC_DIS0_INT13 0x00002000 ///< Interrupt 13 disable
-#define NVIC_DIS0_INT12 0x00001000 ///< Interrupt 12 disable
-#define NVIC_DIS0_INT11 0x00000800 ///< Interrupt 11 disable
-#define NVIC_DIS0_INT10 0x00000400 ///< Interrupt 10 disable
-#define NVIC_DIS0_INT9 0x00000200 ///< Interrupt 9 disable
-#define NVIC_DIS0_INT8 0x00000100 ///< Interrupt 8 disable
-#define NVIC_DIS0_INT7 0x00000080 ///< Interrupt 7 disable
-#define NVIC_DIS0_INT6 0x00000040 ///< Interrupt 6 disable
-#define NVIC_DIS0_INT5 0x00000020 ///< Interrupt 5 disable
-#define NVIC_DIS0_INT4 0x00000010 ///< Interrupt 4 disable
-#define NVIC_DIS0_INT3 0x00000008 ///< Interrupt 3 disable
-#define NVIC_DIS0_INT2 0x00000004 ///< Interrupt 2 disable
-#define NVIC_DIS0_INT1 0x00000002 ///< Interrupt 1 disable
-#define NVIC_DIS0_INT0 0x00000001 ///< Interrupt 0 disable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DIS1 register.
- */
-/*\{*/
-#define NVIC_DIS1_INT59 0x08000000 ///< Interrupt 59 disable
-#define NVIC_DIS1_INT58 0x04000000 ///< Interrupt 58 disable
-#define NVIC_DIS1_INT57 0x02000000 ///< Interrupt 57 disable
-#define NVIC_DIS1_INT56 0x01000000 ///< Interrupt 56 disable
-#define NVIC_DIS1_INT55 0x00800000 ///< Interrupt 55 disable
-#define NVIC_DIS1_INT54 0x00400000 ///< Interrupt 54 disable
-#define NVIC_DIS1_INT53 0x00200000 ///< Interrupt 53 disable
-#define NVIC_DIS1_INT52 0x00100000 ///< Interrupt 52 disable
-#define NVIC_DIS1_INT51 0x00080000 ///< Interrupt 51 disable
-#define NVIC_DIS1_INT50 0x00040000 ///< Interrupt 50 disable
-#define NVIC_DIS1_INT49 0x00020000 ///< Interrupt 49 disable
-#define NVIC_DIS1_INT48 0x00010000 ///< Interrupt 48 disable
-#define NVIC_DIS1_INT47 0x00008000 ///< Interrupt 47 disable
-#define NVIC_DIS1_INT46 0x00004000 ///< Interrupt 46 disable
-#define NVIC_DIS1_INT45 0x00002000 ///< Interrupt 45 disable
-#define NVIC_DIS1_INT44 0x00001000 ///< Interrupt 44 disable
-#define NVIC_DIS1_INT43 0x00000800 ///< Interrupt 43 disable
-#define NVIC_DIS1_INT42 0x00000400 ///< Interrupt 42 disable
-#define NVIC_DIS1_INT41 0x00000200 ///< Interrupt 41 disable
-#define NVIC_DIS1_INT40 0x00000100 ///< Interrupt 40 disable
-#define NVIC_DIS1_INT39 0x00000080 ///< Interrupt 39 disable
-#define NVIC_DIS1_INT38 0x00000040 ///< Interrupt 38 disable
-#define NVIC_DIS1_INT37 0x00000020 ///< Interrupt 37 disable
-#define NVIC_DIS1_INT36 0x00000010 ///< Interrupt 36 disable
-#define NVIC_DIS1_INT35 0x00000008 ///< Interrupt 35 disable
-#define NVIC_DIS1_INT34 0x00000004 ///< Interrupt 34 disable
-#define NVIC_DIS1_INT33 0x00000002 ///< Interrupt 33 disable
-#define NVIC_DIS1_INT32 0x00000001 ///< Interrupt 32 disable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PEND0 register.
- */
-/*\{*/
-#define NVIC_PEND0_INT31 0x80000000 ///< Interrupt 31 pend
-#define NVIC_PEND0_INT30 0x40000000 ///< Interrupt 30 pend
-#define NVIC_PEND0_INT29 0x20000000 ///< Interrupt 29 pend
-#define NVIC_PEND0_INT28 0x10000000 ///< Interrupt 28 pend
-#define NVIC_PEND0_INT27 0x08000000 ///< Interrupt 27 pend
-#define NVIC_PEND0_INT26 0x04000000 ///< Interrupt 26 pend
-#define NVIC_PEND0_INT25 0x02000000 ///< Interrupt 25 pend
-#define NVIC_PEND0_INT24 0x01000000 ///< Interrupt 24 pend
-#define NVIC_PEND0_INT23 0x00800000 ///< Interrupt 23 pend
-#define NVIC_PEND0_INT22 0x00400000 ///< Interrupt 22 pend
-#define NVIC_PEND0_INT21 0x00200000 ///< Interrupt 21 pend
-#define NVIC_PEND0_INT20 0x00100000 ///< Interrupt 20 pend
-#define NVIC_PEND0_INT19 0x00080000 ///< Interrupt 19 pend
-#define NVIC_PEND0_INT18 0x00040000 ///< Interrupt 18 pend
-#define NVIC_PEND0_INT17 0x00020000 ///< Interrupt 17 pend
-#define NVIC_PEND0_INT16 0x00010000 ///< Interrupt 16 pend
-#define NVIC_PEND0_INT15 0x00008000 ///< Interrupt 15 pend
-#define NVIC_PEND0_INT14 0x00004000 ///< Interrupt 14 pend
-#define NVIC_PEND0_INT13 0x00002000 ///< Interrupt 13 pend
-#define NVIC_PEND0_INT12 0x00001000 ///< Interrupt 12 pend
-#define NVIC_PEND0_INT11 0x00000800 ///< Interrupt 11 pend
-#define NVIC_PEND0_INT10 0x00000400 ///< Interrupt 10 pend
-#define NVIC_PEND0_INT9 0x00000200 ///< Interrupt 9 pend
-#define NVIC_PEND0_INT8 0x00000100 ///< Interrupt 8 pend
-#define NVIC_PEND0_INT7 0x00000080 ///< Interrupt 7 pend
-#define NVIC_PEND0_INT6 0x00000040 ///< Interrupt 6 pend
-#define NVIC_PEND0_INT5 0x00000020 ///< Interrupt 5 pend
-#define NVIC_PEND0_INT4 0x00000010 ///< Interrupt 4 pend
-#define NVIC_PEND0_INT3 0x00000008 ///< Interrupt 3 pend
-#define NVIC_PEND0_INT2 0x00000004 ///< Interrupt 2 pend
-#define NVIC_PEND0_INT1 0x00000002 ///< Interrupt 1 pend
-#define NVIC_PEND0_INT0 0x00000001 ///< Interrupt 0 pend
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PEND1 register.
- */
-/*\{*/
-#define NVIC_PEND1_INT59 0x08000000 ///< Interrupt 59 pend
-#define NVIC_PEND1_INT58 0x04000000 ///< Interrupt 58 pend
-#define NVIC_PEND1_INT57 0x02000000 ///< Interrupt 57 pend
-#define NVIC_PEND1_INT56 0x01000000 ///< Interrupt 56 pend
-#define NVIC_PEND1_INT55 0x00800000 ///< Interrupt 55 pend
-#define NVIC_PEND1_INT54 0x00400000 ///< Interrupt 54 pend
-#define NVIC_PEND1_INT53 0x00200000 ///< Interrupt 53 pend
-#define NVIC_PEND1_INT52 0x00100000 ///< Interrupt 52 pend
-#define NVIC_PEND1_INT51 0x00080000 ///< Interrupt 51 pend
-#define NVIC_PEND1_INT50 0x00040000 ///< Interrupt 50 pend
-#define NVIC_PEND1_INT49 0x00020000 ///< Interrupt 49 pend
-#define NVIC_PEND1_INT48 0x00010000 ///< Interrupt 48 pend
-#define NVIC_PEND1_INT47 0x00008000 ///< Interrupt 47 pend
-#define NVIC_PEND1_INT46 0x00004000 ///< Interrupt 46 pend
-#define NVIC_PEND1_INT45 0x00002000 ///< Interrupt 45 pend
-#define NVIC_PEND1_INT44 0x00001000 ///< Interrupt 44 pend
-#define NVIC_PEND1_INT43 0x00000800 ///< Interrupt 43 pend
-#define NVIC_PEND1_INT42 0x00000400 ///< Interrupt 42 pend
-#define NVIC_PEND1_INT41 0x00000200 ///< Interrupt 41 pend
-#define NVIC_PEND1_INT40 0x00000100 ///< Interrupt 40 pend
-#define NVIC_PEND1_INT39 0x00000080 ///< Interrupt 39 pend
-#define NVIC_PEND1_INT38 0x00000040 ///< Interrupt 38 pend
-#define NVIC_PEND1_INT37 0x00000020 ///< Interrupt 37 pend
-#define NVIC_PEND1_INT36 0x00000010 ///< Interrupt 36 pend
-#define NVIC_PEND1_INT35 0x00000008 ///< Interrupt 35 pend
-#define NVIC_PEND1_INT34 0x00000004 ///< Interrupt 34 pend
-#define NVIC_PEND1_INT33 0x00000002 ///< Interrupt 33 pend
-#define NVIC_PEND1_INT32 0x00000001 ///< Interrupt 32 pend
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_UNPEND0 register.
- */
-/*\{*/
-#define NVIC_UNPEND0_INT31 0x80000000 ///< Interrupt 31 unpend
-#define NVIC_UNPEND0_INT30 0x40000000 ///< Interrupt 30 unpend
-#define NVIC_UNPEND0_INT29 0x20000000 ///< Interrupt 29 unpend
-#define NVIC_UNPEND0_INT28 0x10000000 ///< Interrupt 28 unpend
-#define NVIC_UNPEND0_INT27 0x08000000 ///< Interrupt 27 unpend
-#define NVIC_UNPEND0_INT26 0x04000000 ///< Interrupt 26 unpend
-#define NVIC_UNPEND0_INT25 0x02000000 ///< Interrupt 25 unpend
-#define NVIC_UNPEND0_INT24 0x01000000 ///< Interrupt 24 unpend
-#define NVIC_UNPEND0_INT23 0x00800000 ///< Interrupt 23 unpend
-#define NVIC_UNPEND0_INT22 0x00400000 ///< Interrupt 22 unpend
-#define NVIC_UNPEND0_INT21 0x00200000 ///< Interrupt 21 unpend
-#define NVIC_UNPEND0_INT20 0x00100000 ///< Interrupt 20 unpend
-#define NVIC_UNPEND0_INT19 0x00080000 ///< Interrupt 19 unpend
-#define NVIC_UNPEND0_INT18 0x00040000 ///< Interrupt 18 unpend
-#define NVIC_UNPEND0_INT17 0x00020000 ///< Interrupt 17 unpend
-#define NVIC_UNPEND0_INT16 0x00010000 ///< Interrupt 16 unpend
-#define NVIC_UNPEND0_INT15 0x00008000 ///< Interrupt 15 unpend
-#define NVIC_UNPEND0_INT14 0x00004000 ///< Interrupt 14 unpend
-#define NVIC_UNPEND0_INT13 0x00002000 ///< Interrupt 13 unpend
-#define NVIC_UNPEND0_INT12 0x00001000 ///< Interrupt 12 unpend
-#define NVIC_UNPEND0_INT11 0x00000800 ///< Interrupt 11 unpend
-#define NVIC_UNPEND0_INT10 0x00000400 ///< Interrupt 10 unpend
-#define NVIC_UNPEND0_INT9 0x00000200 ///< Interrupt 9 unpend
-#define NVIC_UNPEND0_INT8 0x00000100 ///< Interrupt 8 unpend
-#define NVIC_UNPEND0_INT7 0x00000080 ///< Interrupt 7 unpend
-#define NVIC_UNPEND0_INT6 0x00000040 ///< Interrupt 6 unpend
-#define NVIC_UNPEND0_INT5 0x00000020 ///< Interrupt 5 unpend
-#define NVIC_UNPEND0_INT4 0x00000010 ///< Interrupt 4 unpend
-#define NVIC_UNPEND0_INT3 0x00000008 ///< Interrupt 3 unpend
-#define NVIC_UNPEND0_INT2 0x00000004 ///< Interrupt 2 unpend
-#define NVIC_UNPEND0_INT1 0x00000002 ///< Interrupt 1 unpend
-#define NVIC_UNPEND0_INT0 0x00000001 ///< Interrupt 0 unpend
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_UNPEND1 register.
- */
-/*\{*/
-#define NVIC_UNPEND1_INT59 0x08000000 ///< Interrupt 59 unpend
-#define NVIC_UNPEND1_INT58 0x04000000 ///< Interrupt 58 unpend
-#define NVIC_UNPEND1_INT57 0x02000000 ///< Interrupt 57 unpend
-#define NVIC_UNPEND1_INT56 0x01000000 ///< Interrupt 56 unpend
-#define NVIC_UNPEND1_INT55 0x00800000 ///< Interrupt 55 unpend
-#define NVIC_UNPEND1_INT54 0x00400000 ///< Interrupt 54 unpend
-#define NVIC_UNPEND1_INT53 0x00200000 ///< Interrupt 53 unpend
-#define NVIC_UNPEND1_INT52 0x00100000 ///< Interrupt 52 unpend
-#define NVIC_UNPEND1_INT51 0x00080000 ///< Interrupt 51 unpend
-#define NVIC_UNPEND1_INT50 0x00040000 ///< Interrupt 50 unpend
-#define NVIC_UNPEND1_INT49 0x00020000 ///< Interrupt 49 unpend
-#define NVIC_UNPEND1_INT48 0x00010000 ///< Interrupt 48 unpend
-#define NVIC_UNPEND1_INT47 0x00008000 ///< Interrupt 47 unpend
-#define NVIC_UNPEND1_INT46 0x00004000 ///< Interrupt 46 unpend
-#define NVIC_UNPEND1_INT45 0x00002000 ///< Interrupt 45 unpend
-#define NVIC_UNPEND1_INT44 0x00001000 ///< Interrupt 44 unpend
-#define NVIC_UNPEND1_INT43 0x00000800 ///< Interrupt 43 unpend
-#define NVIC_UNPEND1_INT42 0x00000400 ///< Interrupt 42 unpend
-#define NVIC_UNPEND1_INT41 0x00000200 ///< Interrupt 41 unpend
-#define NVIC_UNPEND1_INT40 0x00000100 ///< Interrupt 40 unpend
-#define NVIC_UNPEND1_INT39 0x00000080 ///< Interrupt 39 unpend
-#define NVIC_UNPEND1_INT38 0x00000040 ///< Interrupt 38 unpend
-#define NVIC_UNPEND1_INT37 0x00000020 ///< Interrupt 37 unpend
-#define NVIC_UNPEND1_INT36 0x00000010 ///< Interrupt 36 unpend
-#define NVIC_UNPEND1_INT35 0x00000008 ///< Interrupt 35 unpend
-#define NVIC_UNPEND1_INT34 0x00000004 ///< Interrupt 34 unpend
-#define NVIC_UNPEND1_INT33 0x00000002 ///< Interrupt 33 unpend
-#define NVIC_UNPEND1_INT32 0x00000001 ///< Interrupt 32 unpend
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_ACTIVE0 register.
- */
-/*\{*/
-#define NVIC_ACTIVE0_INT31 0x80000000 ///< Interrupt 31 active
-#define NVIC_ACTIVE0_INT30 0x40000000 ///< Interrupt 30 active
-#define NVIC_ACTIVE0_INT29 0x20000000 ///< Interrupt 29 active
-#define NVIC_ACTIVE0_INT28 0x10000000 ///< Interrupt 28 active
-#define NVIC_ACTIVE0_INT27 0x08000000 ///< Interrupt 27 active
-#define NVIC_ACTIVE0_INT26 0x04000000 ///< Interrupt 26 active
-#define NVIC_ACTIVE0_INT25 0x02000000 ///< Interrupt 25 active
-#define NVIC_ACTIVE0_INT24 0x01000000 ///< Interrupt 24 active
-#define NVIC_ACTIVE0_INT23 0x00800000 ///< Interrupt 23 active
-#define NVIC_ACTIVE0_INT22 0x00400000 ///< Interrupt 22 active
-#define NVIC_ACTIVE0_INT21 0x00200000 ///< Interrupt 21 active
-#define NVIC_ACTIVE0_INT20 0x00100000 ///< Interrupt 20 active
-#define NVIC_ACTIVE0_INT19 0x00080000 ///< Interrupt 19 active
-#define NVIC_ACTIVE0_INT18 0x00040000 ///< Interrupt 18 active
-#define NVIC_ACTIVE0_INT17 0x00020000 ///< Interrupt 17 active
-#define NVIC_ACTIVE0_INT16 0x00010000 ///< Interrupt 16 active
-#define NVIC_ACTIVE0_INT15 0x00008000 ///< Interrupt 15 active
-#define NVIC_ACTIVE0_INT14 0x00004000 ///< Interrupt 14 active
-#define NVIC_ACTIVE0_INT13 0x00002000 ///< Interrupt 13 active
-#define NVIC_ACTIVE0_INT12 0x00001000 ///< Interrupt 12 active
-#define NVIC_ACTIVE0_INT11 0x00000800 ///< Interrupt 11 active
-#define NVIC_ACTIVE0_INT10 0x00000400 ///< Interrupt 10 active
-#define NVIC_ACTIVE0_INT9 0x00000200 ///< Interrupt 9 active
-#define NVIC_ACTIVE0_INT8 0x00000100 ///< Interrupt 8 active
-#define NVIC_ACTIVE0_INT7 0x00000080 ///< Interrupt 7 active
-#define NVIC_ACTIVE0_INT6 0x00000040 ///< Interrupt 6 active
-#define NVIC_ACTIVE0_INT5 0x00000020 ///< Interrupt 5 active
-#define NVIC_ACTIVE0_INT4 0x00000010 ///< Interrupt 4 active
-#define NVIC_ACTIVE0_INT3 0x00000008 ///< Interrupt 3 active
-#define NVIC_ACTIVE0_INT2 0x00000004 ///< Interrupt 2 active
-#define NVIC_ACTIVE0_INT1 0x00000002 ///< Interrupt 1 active
-#define NVIC_ACTIVE0_INT0 0x00000001 ///< Interrupt 0 active
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_ACTIVE1 register.
- */
-/*\{*/
-#define NVIC_ACTIVE1_INT59 0x08000000 ///< Interrupt 59 active
-#define NVIC_ACTIVE1_INT58 0x04000000 ///< Interrupt 58 active
-#define NVIC_ACTIVE1_INT57 0x02000000 ///< Interrupt 57 active
-#define NVIC_ACTIVE1_INT56 0x01000000 ///< Interrupt 56 active
-#define NVIC_ACTIVE1_INT55 0x00800000 ///< Interrupt 55 active
-#define NVIC_ACTIVE1_INT54 0x00400000 ///< Interrupt 54 active
-#define NVIC_ACTIVE1_INT53 0x00200000 ///< Interrupt 53 active
-#define NVIC_ACTIVE1_INT52 0x00100000 ///< Interrupt 52 active
-#define NVIC_ACTIVE1_INT51 0x00080000 ///< Interrupt 51 active
-#define NVIC_ACTIVE1_INT50 0x00040000 ///< Interrupt 50 active
-#define NVIC_ACTIVE1_INT49 0x00020000 ///< Interrupt 49 active
-#define NVIC_ACTIVE1_INT48 0x00010000 ///< Interrupt 48 active
-#define NVIC_ACTIVE1_INT47 0x00008000 ///< Interrupt 47 active
-#define NVIC_ACTIVE1_INT46 0x00004000 ///< Interrupt 46 active
-#define NVIC_ACTIVE1_INT45 0x00002000 ///< Interrupt 45 active
-#define NVIC_ACTIVE1_INT44 0x00001000 ///< Interrupt 44 active
-#define NVIC_ACTIVE1_INT43 0x00000800 ///< Interrupt 43 active
-#define NVIC_ACTIVE1_INT42 0x00000400 ///< Interrupt 42 active
-#define NVIC_ACTIVE1_INT41 0x00000200 ///< Interrupt 41 active
-#define NVIC_ACTIVE1_INT40 0x00000100 ///< Interrupt 40 active
-#define NVIC_ACTIVE1_INT39 0x00000080 ///< Interrupt 39 active
-#define NVIC_ACTIVE1_INT38 0x00000040 ///< Interrupt 38 active
-#define NVIC_ACTIVE1_INT37 0x00000020 ///< Interrupt 37 active
-#define NVIC_ACTIVE1_INT36 0x00000010 ///< Interrupt 36 active
-#define NVIC_ACTIVE1_INT35 0x00000008 ///< Interrupt 35 active
-#define NVIC_ACTIVE1_INT34 0x00000004 ///< Interrupt 34 active
-#define NVIC_ACTIVE1_INT33 0x00000002 ///< Interrupt 33 active
-#define NVIC_ACTIVE1_INT32 0x00000001 ///< Interrupt 32 active
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI0 register.
- */
-/*\{*/
-#define NVIC_PRI0_INT3_M 0xFF000000 ///< Interrupt 3 priority mask
-#define NVIC_PRI0_INT2_M 0x00FF0000 ///< Interrupt 2 priority mask
-#define NVIC_PRI0_INT1_M 0x0000FF00 ///< Interrupt 1 priority mask
-#define NVIC_PRI0_INT0_M 0x000000FF ///< Interrupt 0 priority mask
-#define NVIC_PRI0_INT3_S 24
-#define NVIC_PRI0_INT2_S 16
-#define NVIC_PRI0_INT1_S 8
-#define NVIC_PRI0_INT0_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI1 register.
- */
-/*\{*/
-#define NVIC_PRI1_INT7_M 0xFF000000 ///< Interrupt 7 priority mask
-#define NVIC_PRI1_INT6_M 0x00FF0000 ///< Interrupt 6 priority mask
-#define NVIC_PRI1_INT5_M 0x0000FF00 ///< Interrupt 5 priority mask
-#define NVIC_PRI1_INT4_M 0x000000FF ///< Interrupt 4 priority mask
-#define NVIC_PRI1_INT7_S 24
-#define NVIC_PRI1_INT6_S 16
-#define NVIC_PRI1_INT5_S 8
-#define NVIC_PRI1_INT4_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI2 register.
- */
-/*\{*/
-#define NVIC_PRI2_INT11_M 0xFF000000 ///< Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M 0x00FF0000 ///< Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M 0x0000FF00 ///< Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M 0x000000FF ///< Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S 24
-#define NVIC_PRI2_INT10_S 16
-#define NVIC_PRI2_INT9_S 8
-#define NVIC_PRI2_INT8_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI3 register.
- */
-/*\{*/
-#define NVIC_PRI3_INT15_M 0xFF000000 ///< Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M 0x00FF0000 ///< Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M 0x0000FF00 ///< Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M 0x000000FF ///< Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S 24
-#define NVIC_PRI3_INT14_S 16
-#define NVIC_PRI3_INT13_S 8
-#define NVIC_PRI3_INT12_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI4 register.
- */
-/*\{*/
-#define NVIC_PRI4_INT19_M 0xFF000000 ///< Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M 0x00FF0000 ///< Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M 0x0000FF00 ///< Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M 0x000000FF ///< Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S 24
-#define NVIC_PRI4_INT18_S 16
-#define NVIC_PRI4_INT17_S 8
-#define NVIC_PRI4_INT16_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI5 register.
- */
-/*\{*/
-#define NVIC_PRI5_INT23_M 0xFF000000 ///< Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M 0x00FF0000 ///< Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M 0x0000FF00 ///< Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M 0x000000FF ///< Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S 24
-#define NVIC_PRI5_INT22_S 16
-#define NVIC_PRI5_INT21_S 8
-#define NVIC_PRI5_INT20_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI6 register.
- */
-/*\{*/
-#define NVIC_PRI6_INT27_M 0xFF000000 ///< Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M 0x00FF0000 ///< Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M 0x0000FF00 ///< Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M 0x000000FF ///< Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S 24
-#define NVIC_PRI6_INT26_S 16
-#define NVIC_PRI6_INT25_S 8
-#define NVIC_PRI6_INT24_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI7 register.
- */
-/*\{*/
-#define NVIC_PRI7_INT31_M 0xFF000000 ///< Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M 0x00FF0000 ///< Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M 0x0000FF00 ///< Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M 0x000000FF ///< Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S 24
-#define NVIC_PRI7_INT30_S 16
-#define NVIC_PRI7_INT29_S 8
-#define NVIC_PRI7_INT28_S 0
-/*\}*/