-/**
- * The following are defines for the bit fields in the NVIC_PRI2 register.
- */
-/*\{*/
-#define NVIC_PRI2_INT11_M 0xFF000000 ///< Interrupt 11 priority mask
-#define NVIC_PRI2_INT10_M 0x00FF0000 ///< Interrupt 10 priority mask
-#define NVIC_PRI2_INT9_M 0x0000FF00 ///< Interrupt 9 priority mask
-#define NVIC_PRI2_INT8_M 0x000000FF ///< Interrupt 8 priority mask
-#define NVIC_PRI2_INT11_S 24
-#define NVIC_PRI2_INT10_S 16
-#define NVIC_PRI2_INT9_S 8
-#define NVIC_PRI2_INT8_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI3 register.
- */
-/*\{*/
-#define NVIC_PRI3_INT15_M 0xFF000000 ///< Interrupt 15 priority mask
-#define NVIC_PRI3_INT14_M 0x00FF0000 ///< Interrupt 14 priority mask
-#define NVIC_PRI3_INT13_M 0x0000FF00 ///< Interrupt 13 priority mask
-#define NVIC_PRI3_INT12_M 0x000000FF ///< Interrupt 12 priority mask
-#define NVIC_PRI3_INT15_S 24
-#define NVIC_PRI3_INT14_S 16
-#define NVIC_PRI3_INT13_S 8
-#define NVIC_PRI3_INT12_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI4 register.
- */
-/*\{*/
-#define NVIC_PRI4_INT19_M 0xFF000000 ///< Interrupt 19 priority mask
-#define NVIC_PRI4_INT18_M 0x00FF0000 ///< Interrupt 18 priority mask
-#define NVIC_PRI4_INT17_M 0x0000FF00 ///< Interrupt 17 priority mask
-#define NVIC_PRI4_INT16_M 0x000000FF ///< Interrupt 16 priority mask
-#define NVIC_PRI4_INT19_S 24
-#define NVIC_PRI4_INT18_S 16
-#define NVIC_PRI4_INT17_S 8
-#define NVIC_PRI4_INT16_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI5 register.
- */
-/*\{*/
-#define NVIC_PRI5_INT23_M 0xFF000000 ///< Interrupt 23 priority mask
-#define NVIC_PRI5_INT22_M 0x00FF0000 ///< Interrupt 22 priority mask
-#define NVIC_PRI5_INT21_M 0x0000FF00 ///< Interrupt 21 priority mask
-#define NVIC_PRI5_INT20_M 0x000000FF ///< Interrupt 20 priority mask
-#define NVIC_PRI5_INT23_S 24
-#define NVIC_PRI5_INT22_S 16
-#define NVIC_PRI5_INT21_S 8
-#define NVIC_PRI5_INT20_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI6 register.
- */
-/*\{*/
-#define NVIC_PRI6_INT27_M 0xFF000000 ///< Interrupt 27 priority mask
-#define NVIC_PRI6_INT26_M 0x00FF0000 ///< Interrupt 26 priority mask
-#define NVIC_PRI6_INT25_M 0x0000FF00 ///< Interrupt 25 priority mask
-#define NVIC_PRI6_INT24_M 0x000000FF ///< Interrupt 24 priority mask
-#define NVIC_PRI6_INT27_S 24
-#define NVIC_PRI6_INT26_S 16
-#define NVIC_PRI6_INT25_S 8
-#define NVIC_PRI6_INT24_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI7 register.
- */
-/*\{*/
-#define NVIC_PRI7_INT31_M 0xFF000000 ///< Interrupt 31 priority mask
-#define NVIC_PRI7_INT30_M 0x00FF0000 ///< Interrupt 30 priority mask
-#define NVIC_PRI7_INT29_M 0x0000FF00 ///< Interrupt 29 priority mask
-#define NVIC_PRI7_INT28_M 0x000000FF ///< Interrupt 28 priority mask
-#define NVIC_PRI7_INT31_S 24
-#define NVIC_PRI7_INT30_S 16
-#define NVIC_PRI7_INT29_S 8
-#define NVIC_PRI7_INT28_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI8 register.
- */
-/*\{*/
-#define NVIC_PRI8_INT35_M 0xFF000000 ///< Interrupt 35 priority mask
-#define NVIC_PRI8_INT34_M 0x00FF0000 ///< Interrupt 34 priority mask
-#define NVIC_PRI8_INT33_M 0x0000FF00 ///< Interrupt 33 priority mask
-#define NVIC_PRI8_INT32_M 0x000000FF ///< Interrupt 32 priority mask
-#define NVIC_PRI8_INT35_S 24
-#define NVIC_PRI8_INT34_S 16
-#define NVIC_PRI8_INT33_S 8
-#define NVIC_PRI8_INT32_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI9 register.
- */
-/*\{*/
-#define NVIC_PRI9_INT39_M 0xFF000000 ///< Interrupt 39 priority mask
-#define NVIC_PRI9_INT38_M 0x00FF0000 ///< Interrupt 38 priority mask
-#define NVIC_PRI9_INT37_M 0x0000FF00 ///< Interrupt 37 priority mask
-#define NVIC_PRI9_INT36_M 0x000000FF ///< Interrupt 36 priority mask
-#define NVIC_PRI9_INT39_S 24
-#define NVIC_PRI9_INT38_S 16
-#define NVIC_PRI9_INT37_S 8
-#define NVIC_PRI9_INT36_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_PRI10 register.
- */
-/*\{*/
-#define NVIC_PRI10_INT43_M 0xFF000000 ///< Interrupt 43 priority mask
-#define NVIC_PRI10_INT42_M 0x00FF0000 ///< Interrupt 42 priority mask
-#define NVIC_PRI10_INT41_M 0x0000FF00 ///< Interrupt 41 priority mask
-#define NVIC_PRI10_INT40_M 0x000000FF ///< Interrupt 40 priority mask
-#define NVIC_PRI10_INT43_S 24
-#define NVIC_PRI10_INT42_S 16
-#define NVIC_PRI10_INT41_S 8
-#define NVIC_PRI10_INT40_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_CPUID register.
- */
-/*\{*/
-#define NVIC_CPUID_IMP_M 0xFF000000 ///< Implementer
-#define NVIC_CPUID_VAR_M 0x00F00000 ///< Variant
-#define NVIC_CPUID_PARTNO_M 0x0000FFF0 ///< Processor part number
-#define NVIC_CPUID_REV_M 0x0000000F ///< Revision
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_INT_CTRL register.
- */
-/*\{*/
-#define NVIC_INT_CTRL_NMI_SET 0x80000000 ///< Pend a NMI
-#define NVIC_INT_CTRL_PEND_SV 0x10000000 ///< Pend a PendSV
-#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 ///< Unpend a PendSV
-#define NVIC_INT_CTRL_PENDSTSET 0x04000000 ///< Set pending SysTick interrupt
-#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 ///< Clear pending SysTick interrupt
-#define NVIC_INT_CTRL_ISR_PRE 0x00800000 ///< Debug interrupt handling
-#define NVIC_INT_CTRL_ISR_PEND 0x00400000 ///< Debug interrupt pending
-#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 ///< Highest pending exception
-#define NVIC_INT_CTRL_RET_BASE 0x00000800 ///< Return to base
-#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF ///< Current active exception
-#define NVIC_INT_CTRL_VEC_PEN_S 12
-#define NVIC_INT_CTRL_VEC_ACT_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_VTABLE register.
- */
-/*\{*/
-#define NVIC_VTABLE_BASE 0x20000000 ///< Vector table base
-#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 ///< Vector table offset
-#define NVIC_VTABLE_OFFSET_S 8
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_APINT register.
- */
-/*\{*/
-#define NVIC_APINT_VECTKEY_M 0xFFFF0000 ///< Vector key mask
-#define NVIC_APINT_VECTKEY 0x05FA0000 ///< Vector key
-#define NVIC_APINT_ENDIANESS 0x00008000 ///< Data endianess
-#define NVIC_APINT_PRIGROUP_M 0x00000700 ///< Priority group
-#define NVIC_APINT_PRIGROUP_0_8 0x00000700 ///< Priority group 0.8 split
-#define NVIC_APINT_PRIGROUP_1_7 0x00000600 ///< Priority group 1.7 split
-#define NVIC_APINT_PRIGROUP_2_6 0x00000500 ///< Priority group 2.6 split
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400 ///< Priority group 3.5 split
-#define NVIC_APINT_PRIGROUP_4_4 0x00000300 ///< Priority group 4.4 split
-#define NVIC_APINT_PRIGROUP_5_3 0x00000200 ///< Priority group 5.3 split
-#define NVIC_APINT_PRIGROUP_6_2 0x00000100 ///< Priority group 6.2 split
-#define NVIC_APINT_SYSRESETREQ 0x00000004 ///< System reset request
-#define NVIC_APINT_VECT_CLR_ACT 0x00000002 ///< Clear active NMI/fault info
-#define NVIC_APINT_VECT_RESET 0x00000001 ///< System reset
-#define NVIC_APINT_PRIGROUP_7_1 0x00000000 ///< Priority group 7.1 split
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_SYS_CTRL register.
- */
-/*\{*/
-#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 ///< Wakeup on pend
-#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 ///< Deep sleep enable
-#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 ///< Sleep on ISR exit
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_CFG_CTRL register.
- */
-/*\{*/
-#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 ///< Ignore bus fault in NMI/fault
-#define NVIC_CFG_CTRL_DIV0 0x00000010 ///< Trap on divide by 0
-#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 ///< Trap on unaligned access
-#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 ///< Allow deep interrupt trigger
-#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 ///< Allow main interrupt trigger
-#define NVIC_CFG_CTRL_BASE_THR 0x00000001 ///< Thread state control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
- */
-/*\{*/
-#define NVIC_SYS_PRI1_RES_M 0xFF000000 ///< Priority of reserved handler
-#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 ///< Priority of usage fault handler
-#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 ///< Priority of bus fault handler
-#define NVIC_SYS_PRI1_MEM_M 0x000000FF ///< Priority of mem manage handler
-#define NVIC_SYS_PRI1_USAGE_S 16
-#define NVIC_SYS_PRI1_BUS_S 8
-#define NVIC_SYS_PRI1_MEM_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
- */
-/*\{*/
-#define NVIC_SYS_PRI2_SVC_M 0xFF000000 ///< Priority of SVCall handler
-#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF ///< Priority of reserved handlers
-#define NVIC_SYS_PRI2_SVC_S 24
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
- */
-/*\{*/
-#define NVIC_SYS_PRI3_TICK_M 0xFF000000 ///< Priority of Sys Tick handler
-#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 ///< Priority of PendSV handler
-#define NVIC_SYS_PRI3_RES_M 0x0000FF00 ///< Priority of reserved handler
-#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF ///< Priority of debug handler
-#define NVIC_SYS_PRI3_TICK_S 24
-#define NVIC_SYS_PRI3_PENDSV_S 16
-#define NVIC_SYS_PRI3_DEBUG_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
-* register.
- */
-/*\{*/
-#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 ///< Usage fault enable
-#define NVIC_SYS_HND_CTRL_BUS 0x00020000 ///< Bus fault enable
-#define NVIC_SYS_HND_CTRL_MEM 0x00010000 ///< Mem manage fault enable
-#define NVIC_SYS_HND_CTRL_SVC 0x00008000 ///< SVCall is pended
-#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 ///< Bus fault is pended
-#define NVIC_SYS_HND_CTRL_TICK 0x00000800 ///< Sys tick is active
-#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 ///< PendSV is active
-#define NVIC_SYS_HND_CTRL_MON 0x00000100 ///< Monitor is active
-#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 ///< SVCall is active
-#define NVIC_SYS_HND_CTRL_USGA 0x00000008 ///< Usage fault is active
-#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 ///< Bus fault is active
-#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 ///< Mem manage is active
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_FAULT_STAT
-* register.
- */
-/*\{*/
-#define NVIC_FAULT_STAT_DIV0 0x02000000 ///< Divide by zero fault
-#define NVIC_FAULT_STAT_UNALIGN 0x01000000 ///< Unaligned access fault
-#define NVIC_FAULT_STAT_NOCP 0x00080000 ///< No coprocessor fault
-#define NVIC_FAULT_STAT_INVPC 0x00040000 ///< Invalid PC fault
-#define NVIC_FAULT_STAT_INVSTAT 0x00020000 ///< Invalid state fault
-#define NVIC_FAULT_STAT_UNDEF 0x00010000 ///< Undefined instruction fault
-#define NVIC_FAULT_STAT_BFARV 0x00008000 ///< BFAR is valid
-#define NVIC_FAULT_STAT_BSTKE 0x00001000 ///< Stack bus fault
-#define NVIC_FAULT_STAT_BUSTKE 0x00000800 ///< Unstack bus fault
-#define NVIC_FAULT_STAT_IMPRE 0x00000400 ///< Imprecise data bus error
-#define NVIC_FAULT_STAT_PRECISE 0x00000200 ///< Precise data bus error
-#define NVIC_FAULT_STAT_IBUS 0x00000100 ///< Instruction bus fault
-#define NVIC_FAULT_STAT_MMARV 0x00000080 ///< MMAR is valid
-#define NVIC_FAULT_STAT_MSTKE 0x00000010 ///< Stack access violation
-#define NVIC_FAULT_STAT_MUSTKE 0x00000008 ///< Unstack access violation
-#define NVIC_FAULT_STAT_DERR 0x00000002 ///< Data access violation
-#define NVIC_FAULT_STAT_IERR 0x00000001 ///< Instruction access violation
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_HFAULT_STAT
-* register.
- */
-/*\{*/
-#define NVIC_HFAULT_STAT_DBG 0x80000000 ///< Debug event
-#define NVIC_HFAULT_STAT_FORCED 0x40000000 ///< Cannot execute fault handler
-#define NVIC_HFAULT_STAT_VECT 0x00000002 ///< Vector table read fault
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DEBUG_STAT
-* register.
- */
-/*\{*/
-#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 ///< EDBGRQ asserted
-#define NVIC_DEBUG_STAT_VCATCH 0x00000008 ///< Vector catch
-#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 ///< DWT match
-#define NVIC_DEBUG_STAT_BKPT 0x00000002 ///< Breakpoint instruction
-#define NVIC_DEBUG_STAT_HALTED 0x00000001 ///< Halt request
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_MM_ADDR register.
- */
-/*\{*/
-#define NVIC_MM_ADDR_M 0xFFFFFFFF ///< Data fault address
-#define NVIC_MM_ADDR_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_FAULT_ADDR
-* register.
- */
-/*\{*/
-#define NVIC_FAULT_ADDR_M 0xFFFFFFFF ///< Data bus fault address
-#define NVIC_FAULT_ADDR_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_MPU_TYPE register.
- */
-/*\{*/
-#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 ///< Number of I regions
-#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 ///< Number of D regions
-#define NVIC_MPU_TYPE_SEPARATE 0x00000001 ///< Separate or unified MPU
-#define NVIC_MPU_TYPE_IREGION_S 16
-#define NVIC_MPU_TYPE_DREGION_S 8
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_MPU_CTRL register.
- */
-/*\{*/
-#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 ///< MPU default region in priv mode
-#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 ///< MPU enabled during faults
-#define NVIC_MPU_CTRL_ENABLE 0x00000001 ///< MPU enable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_MPU_NUMBER
-* register.
- */
-/*\{*/
-#define NVIC_MPU_NUMBER_M 0x000000FF ///< MPU region to access
-#define NVIC_MPU_NUMBER_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_MPU_BASE register.
- */
-/*\{*/
-#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 ///< Base address mask
-#define NVIC_MPU_BASE_VALID 0x00000010 ///< Region number valid
-#define NVIC_MPU_BASE_REGION_M 0x0000000F ///< Region number
-#define NVIC_MPU_BASE_ADDR_S 8
-#define NVIC_MPU_BASE_REGION_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_MPU_ATTR register.
- */
-/*\{*/
-#define NVIC_MPU_ATTR_M 0xFFFF0000 ///< Attributes
-#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 ///< prv: no access, usr: no access
-#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 ///< Bufferable
-#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 ///< Cacheable
-#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 ///< Shareable
-#define NVIC_MPU_ATTR_TEX_M 0x00380000 ///< Type extension mask
-#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 ///< prv: rw, usr: none
-#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 ///< prv: rw, usr: read-only
-#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 ///< prv: rw, usr: rw
-#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 ///< prv: ro, usr: none
-#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 ///< prv: ro, usr: ro
-#define NVIC_MPU_ATTR_AP_M 0x07000000 ///< Access permissions mask
-#define NVIC_MPU_ATTR_XN 0x10000000 ///< Execute disable
-#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 ///< Sub-region disable mask
-#define NVIC_MPU_ATTR_SRD_0 0x00000100 ///< Sub-region 0 disable
-#define NVIC_MPU_ATTR_SRD_1 0x00000200 ///< Sub-region 1 disable
-#define NVIC_MPU_ATTR_SRD_2 0x00000400 ///< Sub-region 2 disable
-#define NVIC_MPU_ATTR_SRD_3 0x00000800 ///< Sub-region 3 disable
-#define NVIC_MPU_ATTR_SRD_4 0x00001000 ///< Sub-region 4 disable
-#define NVIC_MPU_ATTR_SRD_5 0x00002000 ///< Sub-region 5 disable
-#define NVIC_MPU_ATTR_SRD_6 0x00004000 ///< Sub-region 6 disable
-#define NVIC_MPU_ATTR_SRD_7 0x00008000 ///< Sub-region 7 disable
-#define NVIC_MPU_ATTR_SIZE_M 0x0000003E ///< Region size mask
-#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 ///< Region size 32 bytes
-#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A ///< Region size 64 bytes
-#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C ///< Region size 128 bytes
-#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E ///< Region size 256 bytes
-#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 ///< Region size 512 bytes
-#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 ///< Region size 1 Kbytes
-#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 ///< Region size 2 Kbytes
-#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 ///< Region size 4 Kbytes
-#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 ///< Region size 8 Kbytes
-#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A ///< Region size 16 Kbytes
-#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C ///< Region size 32 Kbytes
-#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E ///< Region size 64 Kbytes
-#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 ///< Region size 128 Kbytes
-#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 ///< Region size 256 Kbytes
-#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 ///< Region size 512 Kbytes
-#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 ///< Region size 1 Mbytes
-#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 ///< Region size 2 Mbytes
-#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A ///< Region size 4 Mbytes
-#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C ///< Region size 8 Mbytes
-#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E ///< Region size 16 Mbytes
-#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 ///< Region size 32 Mbytes
-#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 ///< Region size 64 Mbytes
-#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 ///< Region size 128 Mbytes
-#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 ///< Region size 256 Mbytes
-#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 ///< Region size 512 Mbytes
-#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A ///< Region size 1 Gbytes
-#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C ///< Region size 2 Gbytes
-#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E ///< Region size 4 Gbytes
-#define NVIC_MPU_ATTR_ENABLE 0x00000001 ///< Region enable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DBG_CTRL register.
- */
-/*\{*/
-#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 ///< Debug key mask
-#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 ///< Debug key
-#define NVIC_DBG_CTRL_S_RESET_ST \
- 0x02000000 ///< Core has reset since last read
-#define NVIC_DBG_CTRL_S_RETIRE_ST \
- 0x01000000 ///< Core has executed insruction
- ///< since last read
-#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 ///< Core is locked up
-#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 ///< Core is sleeping
-#define NVIC_DBG_CTRL_S_HALT 0x00020000 ///< Core status on halt
-#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 ///< Register read/write available
-#define NVIC_DBG_CTRL_C_SNAPSTALL \
- 0x00000020 ///< Breaks a stalled load/store
-#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 ///< Mask interrupts when stepping
-#define NVIC_DBG_CTRL_C_STEP 0x00000004 ///< Step the core
-#define NVIC_DBG_CTRL_C_HALT 0x00000002 ///< Halt the core
-#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 ///< Enable debug
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DBG_XFER register.
- */
-/*\{*/
-#define NVIC_DBG_XFER_REG_WNR 0x00010000 ///< Write or not read
-#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F ///< Register
-#define NVIC_DBG_XFER_REG_CFBP 0x00000014 ///< Control/Fault/BasePri/PriMask
-#define NVIC_DBG_XFER_REG_DSP 0x00000013 ///< Deep SP
-#define NVIC_DBG_XFER_REG_PSP 0x00000012 ///< Process SP
-#define NVIC_DBG_XFER_REG_MSP 0x00000011 ///< Main SP
-#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 ///< xPSR/Flags register
-#define NVIC_DBG_XFER_REG_R15 0x0000000F ///< Register R15
-#define NVIC_DBG_XFER_REG_R14 0x0000000E ///< Register R14
-#define NVIC_DBG_XFER_REG_R13 0x0000000D ///< Register R13
-#define NVIC_DBG_XFER_REG_R12 0x0000000C ///< Register R12
-#define NVIC_DBG_XFER_REG_R11 0x0000000B ///< Register R11
-#define NVIC_DBG_XFER_REG_R10 0x0000000A ///< Register R10
-#define NVIC_DBG_XFER_REG_R9 0x00000009 ///< Register R9
-#define NVIC_DBG_XFER_REG_R8 0x00000008 ///< Register R8
-#define NVIC_DBG_XFER_REG_R7 0x00000007 ///< Register R7
-#define NVIC_DBG_XFER_REG_R6 0x00000006 ///< Register R6
-#define NVIC_DBG_XFER_REG_R5 0x00000005 ///< Register R5
-#define NVIC_DBG_XFER_REG_R4 0x00000004 ///< Register R4
-#define NVIC_DBG_XFER_REG_R3 0x00000003 ///< Register R3
-#define NVIC_DBG_XFER_REG_R2 0x00000002 ///< Register R2
-#define NVIC_DBG_XFER_REG_R1 0x00000001 ///< Register R1
-#define NVIC_DBG_XFER_REG_R0 0x00000000 ///< Register R0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DBG_DATA register.
- */
-/*\{*/
-#define NVIC_DBG_DATA_M 0xFFFFFFFF ///< Data temporary cache
-#define NVIC_DBG_DATA_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_DBG_INT register.
- */
-/*\{*/
-#define NVIC_DBG_INT_HARDERR 0x00000400 ///< Debug trap on hard fault
-#define NVIC_DBG_INT_INTERR 0x00000200 ///< Debug trap on interrupt errors
-#define NVIC_DBG_INT_BUSERR 0x00000100 ///< Debug trap on bus error
-#define NVIC_DBG_INT_STATERR 0x00000080 ///< Debug trap on usage fault state
-#define NVIC_DBG_INT_CHKERR 0x00000040 ///< Debug trap on usage fault check
-#define NVIC_DBG_INT_NOCPERR 0x00000020 ///< Debug trap on coprocessor error
-#define NVIC_DBG_INT_MMERR 0x00000010 ///< Debug trap on mem manage fault
-#define NVIC_DBG_INT_RESET 0x00000008 ///< Core reset status
-#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 ///< Clear pending core reset
-#define NVIC_DBG_INT_RSTPENDING 0x00000002 ///< Core reset is pending
-#define NVIC_DBG_INT_RSTVCATCH 0x00000001 ///< Reset vector catch
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the NVIC_SW_TRIG register.
- */
-/*\{*/
-#define NVIC_SW_TRIG_INTID_M 0x000003FF ///< Interrupt to trigger
-#define NVIC_SW_TRIG_INTID_S 0
-/*\}*/