-#define DMA_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA_CHANNEL6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0X0000)
+#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0X0008)
+#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0X001C)
+#define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0X0030)
+#define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0X0044)
+#define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0X0058)
+#define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0X006C)
+#define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0X0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0X0400)
+#define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0X0408)
+#define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0X041C)
+#define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0X0430)
+#define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0X0444)
+#define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0X0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0X1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0X3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) ///< Flash registers base address
+
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) ///< FSMC Bank1 registers base address
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) ///< FSMC Bank1E registers base address
+#define FSMC_BANK2_R_BASE (FSMC_R_BASE + 0x0060) ///< FSMC Bank2 registers base address
+#define FSMC_BANK3_R_BASE (FSMC_R_BASE + 0x0080) ///< FSMC Bank3 registers base address
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) ///< FSMC Bank4 registers base address
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) ///< Debug MCU registers base address