+ #define CPU_CM3_STM32F101C4 0
+ #endif
+
+ #if defined (__ARM_STM32F103RB__)
+ #define CPU_CM3_STM32 1
+ #define CPU_CM3_STM32F103RB 1
+ #define CPU_NAME "STM32F103RB"
+ #else
+ #define CPU_CM3_STM32F103RB 0
+ #endif
+
+ #if defined (__ARM_STM32F103RE__)
+ #define CPU_CM3_STM32 1
+ #define CPU_CM3_STM32F103RE 1
+ #define CPU_NAME "STM32F103RE"
+ #else
+ #define CPU_CM3_STM32F103RE 0
+ #endif
+
+ // AT91SAM3N products serie
+ #if defined (__ARM_SAM3N4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3N 1
+ #define CPU_CM3_SAM3N4 1
+ #define CPU_NAME "SAM3N4"
+
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3U 0
+ #define CPU_CM3_SAM3N2 0
+ #define CPU_CM3_SAM3N1 0
+ #define CPU_CM3_SAM3X 0
+ #else
+ #define CPU_CM3_SAM3N4 0
+ #endif
+
+ // AT91SAM3S products serie
+ #if defined (__ARM_SAM3S4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3S 1
+ #define CPU_CM3_SAM3S4 1
+ #define CPU_NAME "SAM3S4"
+
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3U 0
+ #define CPU_CM3_SAM3X 0
+ #else
+ #define CPU_CM3_SAM3S4 0
+ #endif
+
+ // AT91SAM3U products serie
+ #if defined (__ARM_SAM3U4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3U 1
+ #define CPU_CM3_SAM3U4 1
+ #define CPU_NAME "SAM3U4"
+
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3X 0
+ #else
+ #define CPU_CM3_SAM3U4 0
+ #endif
+
+ // AT91SAM3X products serie
+ #if defined (__ARM_SAM3X8__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3X 1
+ #define CPU_CM3_SAM3X8 1
+ #define CPU_NAME "SAM3X8"
+
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3U 0
+ #else
+ #define CPU_CM3_SAM3X8 0