+ #define CPU_ARM_AT91SAM7X512 0
+
+ #define CPU_ARM_LPC2378 0
+#endif
+
+#if defined(__ARM_ARCH_7M__) /* GCC */ \
+ || (defined(__ICCARM__) && (__CORE__== __ARM7M__)) /* IAR: defined for all cores v7M */
+ /* Cortex-M3 */
+ #define CPU_CM3 1
+ #define CPU_ID cm3
+ #define CPU_CORE_NAME "Cortex-M3"
+
+ #if defined (__ARM_LM3S1968__)
+ #define CPU_CM3_LM3S 1
+ #define CPU_CM3_LM3S1968 1
+ #define CPU_NAME "LM3S1968"
+ #else
+ #define CPU_CM3_LM3S1968 0
+ #endif
+
+ #if defined (__ARM_LM3S8962__)
+ #define CPU_CM3_LM3S 1
+ #define CPU_CM3_LM3S8962 1
+ #define CPU_NAME "LM3S8962"
+ #else
+ #define CPU_CM3_LM3S8962 0
+ #endif
+
+ #if defined (__ARM_STM32F101C4__)
+ #define CPU_CM3_STM32 1
+ #define CPU_CM3_STM32F101C4 1
+ #define CPU_NAME "STM32F101C4"
+ #else
+ #define CPU_CM3_STM32F101C4 0
+ #endif
+
+ #if defined (__ARM_STM32F103RB__)
+ #define CPU_CM3_STM32 1
+ #define CPU_CM3_STM32F103RB 1
+ #define CPU_NAME "STM32F103RB"
+ #else
+ #define CPU_CM3_STM32F103RB 0
+ #endif
+
+ #if defined (__ARM_STM32F103RE__)
+ #define CPU_CM3_STM32 1
+ #define CPU_CM3_STM32F103RE 1
+ #define CPU_NAME "STM32F103RE"
+ #else
+ #define CPU_CM3_STM32F103RE 0
+ #endif
+
+ // AT91SAM3N products serie
+ #if defined (__ARM_SAM3N4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3N 1
+ #define CPU_CM3_SAM3N4 1
+ #define CPU_NAME "SAM3N4"
+
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3U 0
+ #define CPU_CM3_SAM3N2 0
+ #define CPU_CM3_SAM3N1 0
+ #define CPU_CM3_SAM3X 0
+ #else
+ #define CPU_CM3_SAM3N4 0
+ #endif
+
+ // AT91SAM3S products serie
+ #if defined (__ARM_SAM3S4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3S 1
+ #define CPU_CM3_SAM3S4 1
+ #define CPU_NAME "SAM3S4"
+
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3U 0
+ #define CPU_CM3_SAM3X 0
+ #else
+ #define CPU_CM3_SAM3S4 0
+ #endif
+
+ // AT91SAM3U products serie
+ #if defined (__ARM_SAM3U4__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3U 1
+ #define CPU_CM3_SAM3U4 1
+ #define CPU_NAME "SAM3U4"
+
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3X 0
+ #else
+ #define CPU_CM3_SAM3U4 0
+ #endif
+
+ // AT91SAM3X products serie
+ #if defined (__ARM_SAM3X8__)
+ #define CPU_CM3_SAM3 1
+ #define CPU_CM3_SAM3X 1
+ #define CPU_CM3_SAM3X8 1
+ #define CPU_NAME "SAM3X8"
+
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3S 0
+ #define CPU_CM3_SAM3U 0
+ #else
+ #define CPU_CM3_SAM3X8 0
+ #endif
+
+ #if defined (CPU_CM3_LM3S)
+ #if CPU_CM3_LM3S1968 + CPU_CM3_LM3S8962 + 0 != 1
+ #error Luminary Cortex-M3 CPU configuration error
+ #endif
+ #define CPU_CM3_STM32 0
+ #define CPU_CM3_SAM3 0
+ #elif defined (CPU_CM3_STM32)
+ #if CPU_CM3_STM32F101C4 + CPU_CM3_STM32F103RB + CPU_CM3_STM32F103RE + 0 != 1
+ #error STM32 Cortex-M3 CPU configuration error
+ #endif
+ #define CPU_CM3_LM3S 0
+ #define CPU_CM3_SAM3 0
+ #elif defined (CPU_CM3_SAM3)
+ #if CPU_CM3_SAM3N + CPU_CM3_SAM3U + CPU_CM3_SAM3S + CPU_CM3_SAM3X + 0 != 1
+ #error SAM3 Cortex-M3 CPU configuration error
+ #endif
+ #if CPU_CM3_SAM3N4 + CPU_CM3_SAM3S4 + CPU_CM3_SAM3U4 + CPU_CM3_SAM3X8 + 0 != 1
+ #error SAM3 Cortex-M3 CPU configuration error
+ #endif
+ #define CPU_CM3_LM3S 0
+ #define CPU_CM3_STM32 0
+ /* #elif Add other Cortex-M3 families here */
+ #else
+ #define CPU_CM3_LM3S 0
+ #define CPU_CM3_STM32 0
+ #define CPU_CM3_SAM3 0
+ #endif
+
+
+ #if CPU_CM3_LM3S + CPU_CM3_STM32 + CPU_CM3_SAM3 + 0 /* Add other Cortex-M3 families here */ != 1
+ #error Cortex-M3 CPU configuration error
+ #endif
+
+#else
+ #define CPU_CM3 0
+ #define CPU_CM3_LM3S 0
+ #define CPU_CM3_LM3S1968 0
+ #define CPU_CM3_LM3S8962 0
+
+ #define CPU_CM3_STM32 0
+ #define CPU_CM3_STM32F103RB 0
+ #define CPU_CM3_STM32F101C4 0
+ #define CPU_CM3_STM32F103RE 0
+
+ #define CPU_CM3_SAM3 0
+ #define CPU_CM3_SAM3N 0
+ #define CPU_CM3_SAM3N4 0
+ #define CPU_CM3_SAM3X 0
+ #define CPU_CM3_SAM3X8 0