- /**
- * Initialization value for registers in stack frame.
- * For the CPSR register, the initial value is set to:
- * - All flags (N, Z, C, V) set to 0.
- * - IRQ and FIQ enabled.
- * - ARM state.
- * - CPU in Supervisor Mode (SVC).
- */
- #define CPU_CREATE_NEW_STACK(stack, entry, exit) \
- do { \
- /* Process entry point */ \
- CPU_PUSH_CALL_FRAME(stack, entry); \
- /* LR (proc_exit) */ \
- CPU_PUSH_CALL_FRAME(stack, exit); \
- /* R11 */ \
- CPU_PUSH_WORD(stack, 0x11111111); \
- /* R10 */ \
- CPU_PUSH_WORD(stack, 0x10101010); \
- /* R9 */ \
- CPU_PUSH_WORD(stack, 0x09090909); \
- /* R8 */ \
- CPU_PUSH_WORD(stack, 0x08080808); \
- /* R7 */ \
- CPU_PUSH_WORD(stack, 0x07070707); \
- /* R6 */ \
- CPU_PUSH_WORD(stack, 0x06060606); \
- /* R5 */ \
- CPU_PUSH_WORD(stack, 0x05050505); \
- /* R4 */ \
- CPU_PUSH_WORD(stack, 0x04040404); \
- /* CPSR */ \
- CPU_PUSH_WORD(stack, 0x00000013); \
- } while (0)
-